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  1. module alu1_test;
  2.     // exhaustively test your 1-bit ALU implementation by adapting mux4_tb.v
  3.     // cycle through all combinations of A and B every 16 time units
  4.     reg A = 0;
  5.     always #1 A = !A;
  6.     reg B = 0;
  7.     always #2 B = !B;
  8.  
  9.     reg [3:0] control = `ALU_ADD;
  10.     reg cin = 0;
  11.     initial begin
  12.         $dumpfile("alu1.vcd");
  13.         $dumpvars(0, alu1_test);
  14.  
  15.         // control is initially ALU_ADD
  16.         # 16 control = `ALU_SUB; // wait 16 time units and then set it to subtract
  17.         # 16 control = `ALU_AND; // wait 16 time units and then set it to and
  18.         # 16 control = `ALU_OR;  // wait 16 time units and then set it to or
  19.         # 16 control = `ALU_NOR; // wait 16 time units and then set it to nor
  20.         # 16 control = `ALU_XOR; // wait 16 time units and then set it to xor
  21.         # 16 $finish; // wait 16 time units and then end the simulation
  22.     end
  23.  
  24.     wire out, cout;
  25.     alu1 a1(out, cout, A, B, cin, control);
  26. endmodule   //alu1_test
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