LIBRARY ieee;
USE ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;




-- Top-level entity
ENTITY poteznysumator IS

PORT ( SW : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
--Clock, Reset, Sel, AddSub : IN STD_LOGIC ;
KEY : IN STD_LOGIC_VECTOR(0 to 3); --Clock, Reset, Sel, AddSub
LEDR : BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0) ;
LEDG: OUT STD_LOGIC ) ;
END poteznysumator ;
ARCHITECTURE Behavior OF poteznysumator IS
SIGNAL G, H, M, Areg, Breg, Zreg, AddSubR_n : STD_LOGIC_VECTOR(7 DOWNTO 0) ;
SIGNAL SelR, AddSubR, carryout, over_flow : STD_LOGIC ;
COMPONENT mux2to1
GENERIC ( k : INTEGER := 8 ) ;
PORT ( V, W : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
Sel : IN STD_LOGIC ;
F : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
END COMPONENT ;
COMPONENT adderk
GENERIC ( k : INTEGER := 8 ) ;
PORT ( carryin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
carryout : OUT STD_LOGIC ) ;
END COMPONENT ;
BEGIN
PROCESS ( KEY(1), KEY(0) )
BEGIN
IF KEY(1) = '1' THEN
Areg <= (OTHERS => '0'); Breg <= (OTHERS => '0');
Zreg <= (OTHERS => '0'); SelR <= '0'; AddSubR <='0'; LEDG <= '0';
ELSIF KEY(0)'EVENT AND KEY(0) = '1' THEN
Areg <= SW(7 downto 0); Breg <= SW(15 downto 8); Zreg <= M;
SelR <= KEY(2); AddSubR <= KEY(3); LEDG <= over_flow;
END IF ;
END PROCESS ;
nbit_adder: adderk
--GENERIC MAP ( k => n )
PORT MAP ( AddSubR, G, H, M, carryout ) ;
multiplexer: mux2to1
--GENERIC MAP ( k => n )
PORT MAP ( Areg, LEDR, SelR, G ) ;
AddSubR_n <= (OTHERS => AddSubR) ;
H <= Breg XOR AddSubR_n ; LEDR <= Zreg ;
over_flow <= carryout XOR G(7) XOR H(7) XOR M(7) ;
END Behavior;
-- k-bit 2-to-1 multiplexer
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY mux2to1 IS
GENERIC ( k : INTEGER := 8 ) ;
PORT ( V, W : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
Sel : IN STD_LOGIC ;
F : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;
END mux2to1 ;
ARCHITECTURE Behavior OF mux2to1 IS
BEGIN
PROCESS ( V, W, Sel )
BEGIN
IF Sel = '0' THEN
F <= V ;
ELSE
F <= W ;
END IF ;
END PROCESS ;
END Behavior ;
-- k-bit adder
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_signed.all ;
ENTITY adderk IS
GENERIC ( k : INTEGER := 8 ) ;
PORT ( carryin : IN STD_LOGIC ;
X, Y : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ;
carryout: OUT STD_LOGIC ) ;
END adderk ;
ARCHITECTURE Behavior OF adderk IS
SIGNAL Sum : STD_LOGIC_VECTOR(8 DOWNTO 0) ;
BEGIN
Sum <= ( '0' & X) + ( '0' & Y) + carryin ;
S <= Sum(7 DOWNTO 0) ;
carryout <= Sum(7) ;
END Behavior ;