library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity taktteiler is


	port (
      clk         : in std_logic; --50 MHz
		clk_10Hz		: out std_logic

		);
end entity taktteiler;

architecture arch of taktteiler is
signal counter : std_logic_vector(22 downto 0);

begin
	process(clk)
	begin

		if(clk ='1' and clk'event) then counter <= std_logic_vector(unsigned(counter) + 1);
		end if;
		if (counter = 010011000100101101000000) then
		clk_10Hz <= not(clk_10Hz);
		counter <= '0';
		end if;

	end process;




end architecture arch;