Bruh

//-----------------------------------------------------------------
// Wishbone BlockRAM
//-----------------------------------------------------------------
//
// Le paramètre mem_adr_width doit permettre de déterminer le nombre
// de mots de la mémoire : (2048 pour mem_adr_width=11)

module wb_bram #(parameter mem_adr_width = 11) (
    // Wishbone interface
    wshb_if.slave wb_s
    );
    // a vous de jouer a partir d'ici
    logic [3:0][7:0] RAM[0:2 ** mem_adr_width - 1];

    wire [mem_adr_width - 1:0] relevant_addr;
    assign relevant_addr = wb_s.adr[mem_adr_width + 1:2];

    assign wb_s.rty = 1'b0;
    assign wb_s.err = 1'b0;

    logic opDone;
    assign wb_s.ack = wb_s.we ? wb_s.cyc && wb_s.stb : opDone;

    always @(posedge wb_s.clk or posedge wb_s.rst)
    begin
        if(wb_s.rst)
        // Handle restart
        begin
            wb_s.dat_sm = 32'd0;
            opDone = 1'b0;
            for(logic [mem_adr_width:0] i = 0; i < 2 ** mem_adr_width - 1; i++)
                RAM[i] = 32'd0;
        end
        else if(opDone)
        // Reset ACK
            opDone = 1'b0;
        else if(wb_s.cyc && wb_s.stb)
        // Handle wishbone
        begin
            if(wb_s.we)
            // Write mode
            begin
                case(wb_s.sel)
                    4'b0001: RAM[relevant_addr][0] = wb_s.dat_ms[7:0];
                    4'b0010: RAM[relevant_addr][1] = wb_s.dat_ms[15:8];
                    4'b0100: RAM[relevant_addr][2] = wb_s.dat_ms[23:16];
                    4'b1000: RAM[relevant_addr][3] = wb_s.dat_ms[31:24];
                    4'b0011: RAM[relevant_addr][1:0] = wb_s.dat_ms[15:0];
                    4'b1100: RAM[relevant_addr][3:2] = wb_s.dat_ms[31:16];
                    4'b1111: RAM[relevant_addr] = wb_s.dat_ms;
                    default: RAM[relevant_addr] = RAM[relevant_addr];
                endcase
            end
            else
            // Read mode
            begin
                case(wb_s.sel)
                    4'b0001: wb_s.dat_sm = RAM[relevant_addr][0];
                    4'b0010: wb_s.dat_sm = RAM[relevant_addr][1] << 8;
                    4'b0100: wb_s.dat_sm = RAM[relevant_addr][2] << 16;
                    4'b1000: wb_s.dat_sm = RAM[relevant_addr][3] << 24;
                    4'b0011: wb_s.dat_sm = RAM[relevant_addr][1:0];
                    4'b1100: wb_s.dat_sm = RAM[relevant_addr][3:2] << 16;
                    4'b1111: wb_s.dat_sm = RAM[relevant_addr];
                    default: wb_s.dat_sm = 32'd0;
                endcase
                opDone = 1'b1;
            end
        end
    end

endmodule