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-- Company:
-- Engineer:
--
-- Create Date: 03/21/2018 12:49:53 PM
-- Design Name:
-- Module Name: SE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity SE is
    Port ( x : in STD_LOGIC;
           y : in STD_LOGIC;
           Tin : in STD_LOGIC;
           Tout : out STD_LOGIC;
           S : out STD_LOGIC);
end SE;

architecture Behavioral of SE is

begin

    S <= x xor y xor Tin;
    Tout <= (x and y) or ((x or y) and Tin);

end Behavioral;