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SallatielFernandes

somador_completo_1bit

Nov 22nd, 2019
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VHDL 0.59 KB | None | 0 0
  1. -- PROJETO: somador_completo_1bit
  2. -- ENTRADA A, B, CIN (tipo bit)
  3. -- SAIDA: SOMA, COUT (tipo bit)
  4. -- AUTORES: MARCOS MEIRA, JOAO VITOR, SALLATIEL TERFERNANDES
  5. -- CRIACAO: 05/12/2018
  6. -- ALTERACAO: 22/11/2019
  7. ----------------------------------------------------------
  8. entity somador_completo_1bit is
  9.     port (A, B, CIN: in bit;
  10.          SOMA, COUT: out bit);
  11. end somador_completo_1bit;
  12. ----------------------------------------------------------
  13. architecture dataflow of somador_completo_1bit is
  14. begin
  15.  
  16.     SOMA <= CIN xor (A xor B);
  17.     COUT <= (A and B) or ((A xor B) and CIN);
  18.  
  19. end dataflow;
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