library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity dc_comp2 is
  port
  ( d      : in std_logic_vector (3 downto 0);
    q      : out std_logic_vector (3 downto 0);
    sign   : out std_logic );
end dc_comp2;




ARCHITECTURE behv OF dc_comp2 IS
signal m0,m1,m2,m3,m4,m5,m6, m7, m8,m9,m10,m11,m12,m13,m14,m15: std_logic;


BEGIN

m0 <= (not d(0) and not d(1) and not d(2) and not d(3));
m1 <= (not d(0) and not d(1) and not d(2) and d(3));
m2 <= (not d(0) and not d(1) and d(2) and not d(3));
m3 <= (not d(0) and not d(1) and d(2) and d(3));
m4 <= (not d(0) and d(1) and not d(2) and not d(3));
m5 <= (not d(0) and d(1) and not d(2) and d(3));
m6 <= (not d(0) and d(1) and d(2) and not d(3));
m7 <= (not d(0) and d(1) and d(2) and d(3));
m8 <= (d(0) and not d(1) and not d(2) and not d(3));
m9 <= (d(0) and not d(1) and not d(2) and d(3));
m10 <= (d(0) and not d(1) and d(2) and not d(3));
m11 <= (d(0) and not d(1) and d(2) and d(3));
m12 <= (d(0) and d(1) and not d(2) and not d(3));
m13 <= (d(0) and d(1) and not d(2) and d(3));
m14 <= (d(0) and d(1) and d(2) and not d(3));
m15 <= (d(0) and d(1) and d(2) and d(3));


 sign <= '1' when ( m8 or m9 or m10 or m11 or m12 or m13 or m14 or m15)
 else '0';
   q(3) <= ( m8);

   q(2) <=  ( m4 or m5 or m6 or m7 or m12 or m9 or m10 or m11) ;

   q(1) <= (m2 or m3 or m6 or m7 or m10 or m14 or m13 or m9);

   q(0) <= (m1 or m3 or m5 or m7 or m9 or m11 or m13 or m15);



END behv;