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- module ControllerTest();
- logic clk, reset;
- logic [5:0] op, funct;
- logic zero;
- logic pcen, memwrite, irwrite, regwrite;
- logic alusrca, iord, memtoreg, regdst;
- logic [1:0] alusrcb, pcsrc;
- logic [2:0] alucontrol;
- logic [10:0] controls;
- initial begin
- reset = 1; #10; reset = 0;
- op = 6'b000010;
- op = 6'b001000; #100;
- op = 6'b000100; #100;
- op = 6'b0; funct = 6'b100000; #100;
- op = 6'b101011; #100;
- funct = 6'b100010; #100;
- funct = 6'b100100; #100;
- op = 6'b100011; #100;
- funct = 6'b100101; #100;
- funct = 6'b101010; #100;
- end
- always begin
- clk = 1; #10; clk = 0; #10;
- end
- controller controler(clk, reset, op, funct, zero, pcen, memwrite, irwrite, regwrite, alusrca,iord,memtoreg,regdst, alusrcb, pcsrc, alucontrol);
- assign controls = {pcen, memwrite, irwrite, regwrite, alusrca, alusrcb, pcsrc, alucontrol};
- endmodule
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