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timurkanaz

Nazarov_circ_1

Jan 10th, 2021
274
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. entity circuit_1 is
  4.     port (  
  5.         pin_name : in STD_LOGIC;
  6.         pin_name1 : in STD_LOGIC;
  7.         pin_name2 : in STD_LOGIC;
  8.         pin_name6 : out STD_LOGIC);
  9. end circuit_1;
  10.  
  11. architecture Behavioral of circuit_1 is
  12. begin
  13.     pin_name6 <= ( (pin_name and (not pin_name1)) or (pin_name1 and pin_name2));
  14. end Behavioral;
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