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  1. typedef struct
  2. {
  3.     std::string name;
  4.     std::string field_name;
  5.     std::string reg_name;
  6.     int         index;
  7.     int         array_index;
  8. } syn_t;
  9.  
  10. std::vector<syn_t> field_syns {
  11.     {"CSR",    "CSR",     "ADC123_Common", 0, -1},
  12.     {"TI0R",   "TIR",     "CAN_TxMailBox", 0, -1},
  13.     {"TDT0R",  "TDTR",    "CAN_TxMailBox", 0, -1},
  14.     {"TDL0R",  "TDLR",    "CAN_TxMailBox", 0, -1},
  15.     {"TDH0R",  "TDHR",    "CAN_TxMailBox", 0, -1},
  16.     {"TI1R",   "TIR",     "CAN_TxMailBox", 1, -1},
  17.     {"TDT1R",  "TDTR",    "CAN_TxMailBox", 1, -1},
  18.     {"TDL1R",  "TDLR",    "CAN_TxMailBox", 1, -1},
  19.     {"TDH1R",  "TDHR",    "CAN_TxMailBox", 1, -1},
  20.     {"TI2R",   "TIR",     "CAN_TxMailBox", 2, -1},
  21.     {"TDT2R",  "TDTR",    "CAN_TxMailBox", 2, -1},
  22.     {"TDL2R",  "TDLR",    "CAN_TxMailBox", 2, -1},
  23.     {"TDH2R",  "TDHR",    "CAN_TxMailBox", 2, -1},
  24.     {"RI0R",   "RIR",     "CAN_FIFOMailBox", 0, -1},
  25.     {"RDT0R",  "RDTR",    "CAN_FIFOMailBox", 0, -1},
  26.     {"RDL0R",  "RDLR",    "CAN_FIFOMailBox", 0, -1},
  27.     {"RDH0R",  "RDHR",    "CAN_FIFOMailBox", 0, -1},
  28.     {"RI1R",   "RIR",     "CAN_FIFOMailBox", 1, -1},
  29.     {"RDT1R",  "RDTR",    "CAN_FIFOMailBox", 1, -1},
  30.     {"RDL1R",  "RDLR",    "CAN_FIFOMailBox", 1, -1},
  31.     {"RDH1R",  "RDHR",    "CAN_FIFOMailBox", 1, -1},
  32.     {"RI2R",   "RIR",     "CAN_FIFOMailBox", 2, -1},
  33.     {"RDT2R",  "RDTR",    "CAN_FIFOMailBox", 2, -1},
  34.     {"RDL2R",  "RDLR",    "CAN_FIFOMailBox", 2, -1},
  35.     {"RDH2R",  "RDHR",    "CAN_FIFOMailBox", 2, -1},
  36.     {"F0R1",   "FR1",     "CAN_FilterRegister", 0, -1},
  37.     {"F0R2",   "FR2",     "CAN_FilterRegister", 0, -1},
  38.     {"F1R1",   "FR1",     "CAN_FilterRegister", 1, -1},
  39.     {"F1R2",   "FR2",     "CAN_FilterRegister", 1, -1},
  40.     {"F2R1",   "FR1",     "CAN_FilterRegister", 2, -1},
  41.     {"F2R2",   "FR2",     "CAN_FilterRegister", 2, -1},
  42.     {"F3R1",   "FR1",     "CAN_FilterRegister", 3, -1},
  43.     {"F3R2",   "FR2",     "CAN_FilterRegister", 3, -1},
  44.     {"F4R1",   "FR1",     "CAN_FilterRegister", 4, -1},
  45.     {"F4R2",   "FR2",     "CAN_FilterRegister", 4, -1},
  46.     {"F5R1",   "FR1",     "CAN_FilterRegister", 5, -1},
  47.     {"F5R2",   "FR2",     "CAN_FilterRegister", 5, -1},
  48.     {"F6R1",   "FR1",     "CAN_FilterRegister", 6, -1},
  49.     {"F6R2",   "FR2",     "CAN_FilterRegister", 6, -1},
  50.     {"F7R1",   "FR1",     "CAN_FilterRegister", 7, -1},
  51.     {"F7R2",   "FR2",     "CAN_FilterRegister", 7, -1},
  52.     {"F8R1",   "FR1",     "CAN_FilterRegister", 8, -1},
  53.     {"F8R2",   "FR2",     "CAN_FilterRegister", 8, -1},
  54.     {"F9R1",   "FR1",     "CAN_FilterRegister", 9, -1},
  55.     {"F9R2",   "FR2",     "CAN_FilterRegister", 9, -1},
  56.     {"F10R1",  "FR1",     "CAN_FilterRegister", 10, -1},
  57.     {"F10R2",  "FR2",     "CAN_FilterRegister", 10, -1},
  58.     {"F11R1",  "FR1",     "CAN_FilterRegister", 11, -1},
  59.     {"F11R2",  "FR2",     "CAN_FilterRegister", 11, -1},
  60.     {"F12R1",  "FR1",     "CAN_FilterRegister", 12, -1},
  61.     {"F12R2",  "FR2",     "CAN_FilterRegister", 12, -1},
  62.     {"F13R1",  "FR1",     "CAN_FilterRegister", 13, -1},
  63.     {"F13R2",  "FR2",     "CAN_FilterRegister", 13, -1},
  64.     {"CWSTRT", "CWSTRTR", "DCMI", 0, -1},
  65.     {"CWSIZE", "CWSIZER", "DCMI", 0, -1},
  66.     {"SxCR",   "CR",      "DMA_Stream", 0, -1},
  67.     {"SxNDT",  "NDTR",    "DMA_Stream", 0, -1},
  68.     {"SxPAR",  "PAR",     "DMA_Stream", 0, -1},
  69.     {"SxM0AR", "M0AR",    "DMA_Stream", 0, -1},
  70.     {"SxM1AR", "M1AR",    "DMA_Stream", 0, -1},
  71.     {"SxFCR",  "FCR",     "DMA_Stream", 0, -1},
  72.     {"BCR1",   "BTCR",    "FSMC_Bank1", 0, 0},
  73.     {"BTR1",   "BTCR",    "FSMC_Bank1", 0, 1},
  74.     {"BCR2",   "BTCR",    "FSMC_Bank1", 0, 2},
  75.     {"BTR2",   "BTCR",    "FSMC_Bank1", 0, 3},
  76.     {"BCR3",   "BTCR",    "FSMC_Bank1", 0, 4},
  77.     {"BTR3",   "BTCR",    "FSMC_Bank1", 0, 5},
  78.     {"BCR4",   "BTCR",    "FSMC_Bank1", 0, 6},
  79.     {"BTR4",   "BTCR",    "FSMC_Bank1", 0, 7},
  80.     {"BWTR1",  "BWTR",    "FSMC_Bank1E", 0, 0},
  81.     {"BWTR2",  "BWTR",    "FSMC_Bank1E", 0, 1},
  82.     {"BWTR3",  "BWTR",    "FSMC_Bank1E", 0, 2},
  83.     {"BWTR4",  "BWTR",    "FSMC_Bank1E", 0, 3},
  84.     {"AFRL",   "AFR",     "GPIO", 0, 0},
  85.     {"AFRH",   "AFR",     "GPIO", 0, 1},
  86.     {"BRR",    "BSRR",    "GPIO", 0, -1},
  87.     {"RESP0",  "RESPCMD", "SDIO", 0, -1},
  88.     {"EXTICR1","EXTICR",  "SYSCFG", 0, 0},
  89.     {"EXTICR2","EXTICR",  "SYSCFG", 0, 1},
  90.     {"EXTICR3","EXTICR",  "SYSCFG", 0, 2},
  91.     {"EXTICR4","EXTICR",  "SYSCFG", 0, 3},
  92.     {"APB1",   "APB1FZ",  "DBGMCU", 0, -1},
  93.     {"APB2",   "APB2FZ",  "DBGMCU", 0, -1},
  94.     {"GOTGCTL","GOTGCTL", "USB_OTG_Global", 0, -1},
  95.     {"GOTGINT","GOTGINT", "USB_OTG_Global", 0, -1},
  96.     {"GAHBCFG","GAHBCFG", "USB_OTG_Global", 0, -1},
  97.     {"GUSBCFG","GUSBCFG", "USB_OTG_Global", 0, -1},
  98.     {"GINTSTS","GINTSTS", "USB_OTG_Global", 0, -1},
  99.     {"GINTMSK","GINTMSK", "USB_OTG_Global", 0, -1},
  100.     {"GRXSTSR","GRXSTSR", "USB_OTG_Global", 0, -1},
  101.     {"GRXSTSP","GRXSTSP", "USB_OTG_Global", 0, -1},
  102.     {"GRXFSIZ","GRXFSIZ", "USB_OTG_Global", 0, -1},
  103.     {"DIEPTXF0_HNPTXFSIZ","DIEPTXF0_HNPTXFSIZ", "USB_OTG_Global", 0, -1},
  104.     {"HNPTXSTS","HNPTXSTS", "USB_OTG_Global", 0, -1},
  105.     {"GCCFG","GCCFG", "USB_OTG_Global", 0, -1},
  106.     {"CID","CID", "USB_OTG_Global", 0, -1},
  107.     {"HPTXFSIZ","HPTXFSIZ", "USB_OTG_Global", 0, -1},
  108.     {"DIEPTXF","DIEPTXF", "USB_OTG_Global", 0, -1},
RAW Paste Data
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