typedef struct
{
    std::string name;
    std::string field_name;
    std::string reg_name;
    int         index;
    int         array_index;
} syn_t;

std::vector<syn_t> field_syns {
    {"CSR",    "CSR",     "ADC123_Common", 0, -1},
    {"TI0R",   "TIR",     "CAN_TxMailBox", 0, -1},
    {"TDT0R",  "TDTR",    "CAN_TxMailBox", 0, -1},
    {"TDL0R",  "TDLR",    "CAN_TxMailBox", 0, -1},
    {"TDH0R",  "TDHR",    "CAN_TxMailBox", 0, -1},
    {"TI1R",   "TIR",     "CAN_TxMailBox", 1, -1},
    {"TDT1R",  "TDTR",    "CAN_TxMailBox", 1, -1},
    {"TDL1R",  "TDLR",    "CAN_TxMailBox", 1, -1},
    {"TDH1R",  "TDHR",    "CAN_TxMailBox", 1, -1},
    {"TI2R",   "TIR",     "CAN_TxMailBox", 2, -1},
    {"TDT2R",  "TDTR",    "CAN_TxMailBox", 2, -1},
    {"TDL2R",  "TDLR",    "CAN_TxMailBox", 2, -1},
    {"TDH2R",  "TDHR",    "CAN_TxMailBox", 2, -1},
    {"RI0R",   "RIR",     "CAN_FIFOMailBox", 0, -1},
    {"RDT0R",  "RDTR",    "CAN_FIFOMailBox", 0, -1},
    {"RDL0R",  "RDLR",    "CAN_FIFOMailBox", 0, -1},
    {"RDH0R",  "RDHR",    "CAN_FIFOMailBox", 0, -1},
    {"RI1R",   "RIR",     "CAN_FIFOMailBox", 1, -1},
    {"RDT1R",  "RDTR",    "CAN_FIFOMailBox", 1, -1},
    {"RDL1R",  "RDLR",    "CAN_FIFOMailBox", 1, -1},
    {"RDH1R",  "RDHR",    "CAN_FIFOMailBox", 1, -1},
    {"RI2R",   "RIR",     "CAN_FIFOMailBox", 2, -1},
    {"RDT2R",  "RDTR",    "CAN_FIFOMailBox", 2, -1},
    {"RDL2R",  "RDLR",    "CAN_FIFOMailBox", 2, -1},
    {"RDH2R",  "RDHR",    "CAN_FIFOMailBox", 2, -1},
    {"F0R1",   "FR1",     "CAN_FilterRegister", 0, -1},
    {"F0R2",   "FR2",     "CAN_FilterRegister", 0, -1},
    {"F1R1",   "FR1",     "CAN_FilterRegister", 1, -1},
    {"F1R2",   "FR2",     "CAN_FilterRegister", 1, -1},
    {"F2R1",   "FR1",     "CAN_FilterRegister", 2, -1},
    {"F2R2",   "FR2",     "CAN_FilterRegister", 2, -1},
    {"F3R1",   "FR1",     "CAN_FilterRegister", 3, -1},
    {"F3R2",   "FR2",     "CAN_FilterRegister", 3, -1},
    {"F4R1",   "FR1",     "CAN_FilterRegister", 4, -1},
    {"F4R2",   "FR2",     "CAN_FilterRegister", 4, -1},
    {"F5R1",   "FR1",     "CAN_FilterRegister", 5, -1},
    {"F5R2",   "FR2",     "CAN_FilterRegister", 5, -1},
    {"F6R1",   "FR1",     "CAN_FilterRegister", 6, -1},
    {"F6R2",   "FR2",     "CAN_FilterRegister", 6, -1},
    {"F7R1",   "FR1",     "CAN_FilterRegister", 7, -1},
    {"F7R2",   "FR2",     "CAN_FilterRegister", 7, -1},
    {"F8R1",   "FR1",     "CAN_FilterRegister", 8, -1},
    {"F8R2",   "FR2",     "CAN_FilterRegister", 8, -1},
    {"F9R1",   "FR1",     "CAN_FilterRegister", 9, -1},
    {"F9R2",   "FR2",     "CAN_FilterRegister", 9, -1},
    {"F10R1",  "FR1",     "CAN_FilterRegister", 10, -1},
    {"F10R2",  "FR2",     "CAN_FilterRegister", 10, -1},
    {"F11R1",  "FR1",     "CAN_FilterRegister", 11, -1},
    {"F11R2",  "FR2",     "CAN_FilterRegister", 11, -1},
    {"F12R1",  "FR1",     "CAN_FilterRegister", 12, -1},
    {"F12R2",  "FR2",     "CAN_FilterRegister", 12, -1},
    {"F13R1",  "FR1",     "CAN_FilterRegister", 13, -1},
    {"F13R2",  "FR2",     "CAN_FilterRegister", 13, -1},
    {"CWSTRT", "CWSTRTR", "DCMI", 0, -1},
    {"CWSIZE", "CWSIZER", "DCMI", 0, -1},
    {"SxCR",   "CR",      "DMA_Stream", 0, -1},
    {"SxNDT",  "NDTR",    "DMA_Stream", 0, -1},
    {"SxPAR",  "PAR",     "DMA_Stream", 0, -1},
    {"SxM0AR", "M0AR",    "DMA_Stream", 0, -1},
    {"SxM1AR", "M1AR",    "DMA_Stream", 0, -1},
    {"SxFCR",  "FCR",     "DMA_Stream", 0, -1},
    {"BCR1",   "BTCR",    "FSMC_Bank1", 0, 0},
    {"BTR1",   "BTCR",    "FSMC_Bank1", 0, 1},
    {"BCR2",   "BTCR",    "FSMC_Bank1", 0, 2},
    {"BTR2",   "BTCR",    "FSMC_Bank1", 0, 3},
    {"BCR3",   "BTCR",    "FSMC_Bank1", 0, 4},
    {"BTR3",   "BTCR",    "FSMC_Bank1", 0, 5},
    {"BCR4",   "BTCR",    "FSMC_Bank1", 0, 6},
    {"BTR4",   "BTCR",    "FSMC_Bank1", 0, 7},
    {"BWTR1",  "BWTR",    "FSMC_Bank1E", 0, 0},
    {"BWTR2",  "BWTR",    "FSMC_Bank1E", 0, 1},
    {"BWTR3",  "BWTR",    "FSMC_Bank1E", 0, 2},
    {"BWTR4",  "BWTR",    "FSMC_Bank1E", 0, 3},
    {"AFRL",   "AFR",     "GPIO", 0, 0},
    {"AFRH",   "AFR",     "GPIO", 0, 1},
    {"BRR",    "BSRR",    "GPIO", 0, -1},
    {"RESP0",  "RESPCMD", "SDIO", 0, -1},
    {"EXTICR1","EXTICR",  "SYSCFG", 0, 0},
    {"EXTICR2","EXTICR",  "SYSCFG", 0, 1},
    {"EXTICR3","EXTICR",  "SYSCFG", 0, 2},
    {"EXTICR4","EXTICR",  "SYSCFG", 0, 3},
    {"APB1",   "APB1FZ",  "DBGMCU", 0, -1},
    {"APB2",   "APB2FZ",  "DBGMCU", 0, -1},
    {"GOTGCTL","GOTGCTL", "USB_OTG_Global", 0, -1},
    {"GOTGINT","GOTGINT", "USB_OTG_Global", 0, -1},
    {"GAHBCFG","GAHBCFG", "USB_OTG_Global", 0, -1},
    {"GUSBCFG","GUSBCFG", "USB_OTG_Global", 0, -1},
    {"GINTSTS","GINTSTS", "USB_OTG_Global", 0, -1},
    {"GINTMSK","GINTMSK", "USB_OTG_Global", 0, -1},
    {"GRXSTSR","GRXSTSR", "USB_OTG_Global", 0, -1},
    {"GRXSTSP","GRXSTSP", "USB_OTG_Global", 0, -1},
    {"GRXFSIZ","GRXFSIZ", "USB_OTG_Global", 0, -1},
    {"DIEPTXF0_HNPTXFSIZ","DIEPTXF0_HNPTXFSIZ", "USB_OTG_Global", 0, -1},
    {"HNPTXSTS","HNPTXSTS", "USB_OTG_Global", 0, -1},
    {"GCCFG","GCCFG", "USB_OTG_Global", 0, -1},
    {"CID","CID", "USB_OTG_Global", 0, -1},
    {"HPTXFSIZ","HPTXFSIZ", "USB_OTG_Global", 0, -1},
    {"DIEPTXF","DIEPTXF", "USB_OTG_Global", 0, -1},