library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity vjezba_tb is
end entity;

architecture Test_tb of vjezba_tb is

    signal sA : std_logic_vector(2 downto 0 );
    signal sB : std_logic_vector(4 downto 0 );
    signal sC : std_logic_vector(7 downto 0 );
    signal sSEL : std_logic_vector(3 downto 0 );
    signal sRESULT : std_logic_vector(7 downto 0);

component vjezba is
    port (
        iA : in std_logic_vector(2 downto 0 );
        iB : in std_logic_vector(4 downto 0 );
        iC : in std_logic_vector(7 downto 0 );
        iSEL : in std_logic_vector(3 downto 0 );
        oRESULT : out std_logic_vector(7 downto 0)

    );
    end component;

    begin

    uut: vjezba port map(
        iA => sA,
        iB => sB,
        iC => sC,
        iSEL => sSEL,
        oRESULT => sRESULT
    );

    stimulus: process
    begin

    sA<= "111";
    sB <= "00001";
    sC <= "10110101";
    sSEL <= "0001";
    wait;

    end process;
end architecture;