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  1. ----------------------------------------------------------------------------------
  2. -- Company:
  3. -- Engineer:
  4. --
  5. -- Create Date:    15:39:30 10/10/2016
  6. -- Design Name:
  7. -- Module Name:    decoder - Behavioral
  8. -- Project Name:
  9. -- Target Devices:
  10. -- Tool versions:
  11. -- Description:
  12. --
  13. -- Dependencies:
  14. --
  15. -- Revision:
  16. -- Revision 0.01 - File Created
  17. -- Additional Comments:
  18. --
  19. ----------------------------------------------------------------------------------
  20. library IEEE;
  21. use IEEE.STD_LOGIC_1164.ALL;
  22. use IEEE.STD_LOGIC_ARITH.ALL;
  23. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  24.  
  25. ---- Uncomment the following library declaration if instantiating
  26. ---- any Xilinx primitives in this code.
  27. --library UNISIM;
  28. --use UNISIM.VComponents.all;
  29.  
  30. entity decoder is
  31.     Port ( bitz_i : in  STD_LOGIC_VECTOR (3 downto 0);
  32.            num_o : out  STD_LOGIC_VECTOR (7 downto 0));
  33. end decoder;
  34.  
  35. architecture Behavioral of decoder is
  36.  
  37. begin
  38.  
  39. with bitz_i select num_o <=
  40.         "00000011" when "0000",
  41.         "10011111" when "0001",
  42.         "00100101" when "0010",
  43.         "00001101" when "0011",
  44.         "10011001" when "0100",
  45.         "01001001" when "0101",
  46.         "01000001" when "0110",
  47.         "00011111" when "0111",
  48.         "00000001" when "1000",
  49.         "00001001" when "1001",
  50.         "00010001" when "1010",
  51.         "11000001" when "1011",
  52.         "01100011" when "1100",
  53.         "10000101" when "1101",
  54.         "01100001" when "1110",
  55.         "01110001" when "1111",
  56.         "11111111" when others;
  57.  
  58. end Behavioral;
  59.  
  60. ########################################################################################################
  61.  
  62. ----------------------------------------------------------------------------------
  63. -- Company:
  64. -- Engineer:
  65. --
  66. -- Create Date:    14:22:12 10/03/2016
  67. -- Design Name:
  68. -- Module Name:    led_sterownik - Behavioral
  69. -- Project Name:
  70. -- Target Devices:
  71. -- Tool versions:
  72. -- Description:
  73. --
  74. -- Dependencies:
  75. --
  76. -- Revision:
  77. -- Revision 0.01 - File Created
  78. -- Additional Comments:
  79. --
  80. ----------------------------------------------------------------------------------
  81. library IEEE;
  82. use IEEE.STD_LOGIC_1164.ALL;
  83. use IEEE.STD_LOGIC_ARITH.ALL;
  84. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  85.  
  86. ---- Uncomment the following library declaration if instantiating
  87. ---- any Xilinx primitives in this code.
  88. --library UNISIM;
  89. --use UNISIM.VComponents.all;
  90.  
  91. entity led_sterownik is
  92.     Port ( clk_i : in  STD_LOGIC;
  93.            rst_i : in  STD_LOGIC;
  94.            digit_i : in  STD_LOGIC_VECTOR (31 downto 0);
  95.            led7_an_o : out  STD_LOGIC_VECTOR (3 downto 0);
  96.            led7_seg_o : out  STD_LOGIC_VECTOR (7 downto 0));
  97. end led_sterownik;
  98.  
  99. architecture Behavioral of led_sterownik is
  100.  
  101. -- aktywny pierwszy segment
  102. signal aktywny_segment : STD_LOGIC_VECTOR (3 downto 0) := "0111";
  103. signal kodzik : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
  104. constant podzial_zegara : INTEGER := 50000;
  105.  
  106. begin
  107.     mux: process(clk_i) is
  108.         variable x: integer := 0;
  109.         begin
  110.             if rising_edge(clk_i) then
  111.                 x := x + 1;
  112.                 if x = podzial_zegara then
  113.                     case aktywny_segment is
  114.                         when "0111" => aktywny_segment <= "1011";
  115.                         when "1011" => aktywny_segment <= "1101";
  116.                         when "1101" => aktywny_segment <= "1110";
  117.                         when "1110" => aktywny_segment <= "0111";
  118.                         when others => aktywny_segment <= "0111";
  119.                     end case;
  120.                     x := 0;
  121.                 end if;
  122.             end if;
  123.         end process;
  124.     led7_seg_o <= kodzik;
  125.     led7_an_o <= aktywny_segment;
  126.     with aktywny_segment select kodzik <=
  127.         digit_i(31 downto 24) when "0111",
  128.         digit_i(23 downto 16) when "1011",
  129.         digit_i(15 downto 8) when "1101",
  130.         digit_i(7 downto 0) when "1110",
  131.         "00000000" when others;
  132. end Behavioral;
  133.  
  134. ########################################################################################################
  135.  
  136. ----------------------------------------------------------------------------------
  137. -- Company:
  138. -- Engineer:
  139. --
  140. -- Create Date:    14:24:34 10/03/2016
  141. -- Design Name:
  142. -- Module Name:    odbiornik - Behavioral
  143. -- Project Name:
  144. -- Target Devices:
  145. -- Tool versions:
  146. -- Description:
  147. --
  148. -- Dependencies:
  149. --
  150. -- Revision:
  151. -- Revision 0.01 - File Created
  152. -- Additional Comments:
  153. --
  154. ----------------------------------------------------------------------------------
  155. library IEEE;
  156. use IEEE.STD_LOGIC_1164.ALL;
  157. use IEEE.STD_LOGIC_ARITH.ALL;
  158. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  159.  
  160. ---- Uncomment the following library declaration if instantiating
  161. ---- any Xilinx primitives in this code.
  162. --library UNISIM;
  163. --use UNISIM.VComponents.all;
  164.  
  165. entity odbiornik is
  166.     Port ( clk_i : in  STD_LOGIC;
  167.            RXD_i : in  STD_LOGIC;
  168.            digit_o : out  STD_LOGIC_VECTOR (15 downto 0));
  169. end odbiornik;
  170.  
  171. architecture Behavioral of odbiornik is
  172.  
  173. COMPONENT decoder
  174.     Port ( bitz_i : in  STD_LOGIC_VECTOR (3 downto 0);
  175.            num_o : out  STD_LOGIC_VECTOR (7 downto 0));
  176.    END COMPONENT;
  177.  
  178. signal starszy_nib : STD_LOGIC_VECTOR(3 downto 0);
  179. signal mlodszy_nib : STD_LOGIC_VECTOR(3 downto 0);
  180. signal RXD_internal : STD_LOGIC;
  181.  
  182. type StateType is (idle, waitforit, recivin, finishin);
  183. signal present_state : StateType;
  184. signal next_state : StateType;
  185. begin
  186.  
  187.     buforek_odbiorek : process (clk_i) is
  188.     begin
  189.         if rising_edge(clk_i) then
  190.             RXD_internal <= RXD_i;
  191.         end if;
  192.     end process;
  193.    
  194.     stejt_machina_komb : process (clk_i) is
  195.     variable recvcount : integer := 0;
  196.     variable x : integer := 0;
  197.     begin
  198.         if rising_edge(clk_i) then
  199.             present_state <= next_state;
  200.             case present_state is
  201.                 when idle =>
  202.                     if RXD_internal = '0' then
  203.                         next_state <= waitforit;
  204.                         x := 0;
  205.                     end if;
  206.                 when waitforit =>
  207.                     x := x + 1;
  208.                     if x = 2604 then
  209.                         if RXD_internal = '0' then
  210.                             next_state <= recivin;
  211.                         else
  212.                             next_state <= idle;
  213.                         end if;
  214.                         x := 0;
  215.                     end if;
  216.                 when recivin =>
  217.                     x := x + 1;
  218.                     if x = 5208 then
  219.                         if recvcount = 8 then
  220.                             next_state <= finishin;
  221.                         elsif recvcount < 4 then
  222.                             mlodszy_nib(recvcount) <= RXD_internal;
  223.                             recvcount := recvcount + 1;
  224.                         elsif recvcount < 8 then
  225.                             starszy_nib(recvcount-4) <= RXD_internal;
  226.                             recvcount := recvcount + 1;
  227.                         end if;
  228.                         x := 0;
  229.                     end if;
  230.                 when finishin =>
  231.                         x := 0;
  232.                         recvcount := 0;
  233.                         next_state <= idle;
  234.                 end case;
  235.             end if;
  236.         end process;
  237.    
  238.  
  239.     nibble1 : decoder port map (starszy_nib, digit_o(15 downto 8));
  240.     nibble2 : decoder port map (mlodszy_nib, digit_o(7 downto 0));
  241.    
  242. end Behavioral;
  243.  
  244. ########################################################################################################
  245.  
  246. --------------------------------------------------------------------------------
  247. -- Company:
  248. -- Engineer:
  249. --
  250. -- Create Date:   14:34:22 10/17/2016
  251. -- Design Name:  
  252. -- Module Name:   /home/lab526/lab4/tb.vhd
  253. -- Project Name:  lab4
  254. -- Target Device:  
  255. -- Tool versions:  
  256. -- Description:  
  257. --
  258. -- VHDL Test Bench Created by ISE for module: top
  259. --
  260. -- Dependencies:
  261. --
  262. -- Revision:
  263. -- Revision 0.01 - File Created
  264. -- Additional Comments:
  265. --
  266. -- Notes:
  267. -- This testbench has been automatically generated using types std_logic and
  268. -- std_logic_vector for the ports of the unit under test.  Xilinx recommends
  269. -- that these types always be used for the top-level I/O of a design in order
  270. -- to guarantee that the testbench will bind correctly to the post-implementation
  271. -- simulation model.
  272. --------------------------------------------------------------------------------
  273. LIBRARY ieee;
  274. USE ieee.std_logic_1164.ALL;
  275. USE ieee.std_logic_unsigned.all;
  276. USE ieee.numeric_std.ALL;
  277.  
  278. ENTITY tb IS
  279. END tb;
  280.  
  281. ARCHITECTURE behavior OF tb IS
  282.  
  283.     -- Component Declaration for the Unit Under Test (UUT)
  284.  
  285.     COMPONENT top
  286.     PORT(
  287.          clk_i : IN  std_logic;
  288.          rst_i : IN  std_logic;
  289.          RXD_i : IN  std_logic;
  290.          led7_an_o : OUT  std_logic_vector(3 downto 0);
  291.          led7_seg_o : OUT  std_logic_vector(7 downto 0)
  292.         );
  293.     END COMPONENT;
  294.    
  295.  
  296.    --Inputs
  297.    signal clk_i : std_logic := '0';
  298.    signal rst_i : std_logic := '0';
  299.    signal RXD_i : std_logic := '1';
  300.  
  301.     --Outputs
  302.    signal led7_an_o : std_logic_vector(3 downto 0);
  303.    signal led7_seg_o : std_logic_vector(7 downto 0);
  304.  
  305.    -- Clock period definitions
  306.    constant clk_i_period : time := 20ns;
  307.  
  308. BEGIN
  309.  
  310.     -- Instantiate the Unit Under Test (UUT)
  311.    uut: top PORT MAP (
  312.           clk_i => clk_i,
  313.           rst_i => rst_i,
  314.           RXD_i => RXD_i,
  315.           led7_an_o => led7_an_o,
  316.           led7_seg_o => led7_seg_o
  317.         );
  318.  
  319.    -- Clock process definitions
  320.    clk_i_process :process
  321.    begin
  322.         clk_i <= '0';
  323.         wait for clk_i_period/2;
  324.         clk_i <= '1';
  325.         wait for clk_i_period/2;
  326.    end process;
  327.  
  328.  
  329.    -- Stimulus process
  330.    stim_proc: process
  331.    begin       
  332.       -- hold reset state for 100ms.
  333.       wait for 10ms;   
  334.       wait for clk_i_period*10;
  335.       -- insert stimulus here
  336.         RXD_i <= '0';
  337.         wait for 101us;
  338.         RXD_i <= '1';
  339.         wait for 101us;
  340.         RXD_i <= '1';
  341.         wait for 101us;
  342.         RXD_i <= '1';
  343.         wait for 101us;
  344.         RXD_i <= '1';
  345.         wait for 101us;
  346.         RXD_i <= '0';
  347.         wait for 101us;
  348.         RXD_i <= '0';
  349.         wait for 101us;
  350.         RXD_i <= '0';
  351.         wait for 101us;
  352.         RXD_i <= '0';
  353.         wait for 101us;
  354.         RXD_i <= '1';
  355.       wait;
  356.    end process;
  357.  
  358. END;
  359.  
  360. ########################################################################################################
  361.  
  362. ----------------------------------------------------------------------------------
  363. -- Company:
  364. -- Engineer:
  365. --
  366. -- Create Date:    14:31:59 10/10/2016
  367. -- Design Name:
  368. -- Module Name:    top - Behavioral
  369. -- Project Name:
  370. -- Target Devices:
  371. -- Tool versions:
  372. -- Description:
  373. --
  374. -- Dependencies:
  375. --
  376. -- Revision:
  377. -- Revision 0.01 - File Created
  378. -- Additional Comments:
  379. --
  380. ----------------------------------------------------------------------------------
  381. library IEEE;
  382. use IEEE.STD_LOGIC_1164.ALL;
  383. use IEEE.STD_LOGIC_ARITH.ALL;
  384. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  385.  
  386. ---- Uncomment the following library declaration if instantiating
  387. ---- any Xilinx primitives in this code.
  388. --library UNISIM;
  389. --use UNISIM.VComponents.all;
  390.  
  391. entity top is
  392.     Port ( clk_i : in  STD_LOGIC;
  393.            rst_i : in  STD_LOGIC;
  394.            RXD_i : in  STD_LOGIC;
  395.            led7_an_o : out  STD_LOGIC_VECTOR (3 downto 0);
  396.            led7_seg_o : out  STD_LOGIC_VECTOR (7 downto 0));
  397. end top;
  398.  
  399. architecture Behavioral of top is
  400.  
  401.     COMPONENT led_sterownik
  402.     Port ( clk_i : in  STD_LOGIC;
  403.            rst_i : in  STD_LOGIC;
  404.            digit_i : in  STD_LOGIC_VECTOR (31 downto 0);
  405.            led7_an_o : out  STD_LOGIC_VECTOR (3 downto 0);
  406.            led7_seg_o : out  STD_LOGIC_VECTOR (7 downto 0));
  407.    END COMPONENT;
  408.    
  409.     COMPONENT odbiornik
  410.     Port (  clk_i : in  STD_LOGIC;
  411.                 RXD_i : in STD_LOGIC;
  412.                 digit_o : out  STD_LOGIC_VECTOR (15 downto 0));
  413.    END COMPONENT;
  414.    
  415.     signal digitz : STD_LOGIC_VECTOR (31 downto 0);
  416.     signal recieved : STD_LOGIC_VECTOR(15 downto 0);
  417.  
  418. begin
  419.  
  420.    led_ster: led_sterownik PORT MAP (clk_i, '0', digitz, led7_an_o, led7_seg_o);
  421.    obornik: odbiornik PORT MAP (clk_i,RXD_i,recieved);
  422.     digitz(31 downto 16) <= "1111111111111111";
  423.     digitz(15 downto 0) <= recieved;
  424. end Behavioral;
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