LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY ROP IS
    PORT (
        CLOCK    : IN STD_LOGIC;
        BT1      : IN STD_LOGIC;
        BT2      : IN STD_LOGIC;
        SWITCHES : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
        INST     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
    );
END ROP;

ARCHITECTURE BEHAVIOR OF ROP IS
BEGIN
    PROCESS(CLOCK,BT1,BT2)
    BEGIN
        IF CLOCK'EVENT AND CLOCK = '1' THEN
            IF BT1 = '1' THEN
                INST(15 DOWNTO 0) <= SWITCHES;
            END IF;

            IF BT2 = '1' THEN
                INST(31 DOWNTO 16) <= SWITCHES;
            END IF;
        END IF;
    END PROCESS;
END BEHAVIOR;