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  1. WARNING
  2. This patch works with gcc versions 4.9+ and with kernel version 4.13+ and should
  3. NOT be applied when compiling on older versions of gcc due to key name changes
  4. of the march flags introduced with the version 4.9 release of gcc.[1]
  5.  
  6. Use the older version of this patch hosted on the same github for older
  7. versions of gcc.
  8.  
  9. FEATURES
  10. This patch adds additional CPU options to the Linux kernel accessible under:
  11. Processor type and features --->
  12. Processor family --->
  13.  
  14. The expanded microarchitectures include:
  15. * AMD Improved K8-family
  16. * AMD K10-family
  17. * AMD Family 10h (Barcelona)
  18. * AMD Family 14h (Bobcat)
  19. * AMD Family 16h (Jaguar)
  20. * AMD Family 15h (Bulldozer)
  21. * AMD Family 15h (Piledriver)
  22. * AMD Family 15h (Steamroller)
  23. * AMD Family 15h (Excavator)
  24. * AMD Family 17h (Zen)
  25. * Intel Silvermont low-power processors
  26. * Intel 1st Gen Core i3/i5/i7 (Nehalem)
  27. * Intel 1.5 Gen Core i3/i5/i7 (Westmere)
  28. * Intel 2nd Gen Core i3/i5/i7 (Sandybridge)
  29. * Intel 3rd Gen Core i3/i5/i7 (Ivybridge)
  30. * Intel 4th Gen Core i3/i5/i7 (Haswell)
  31. * Intel 5th Gen Core i3/i5/i7 (Broadwell)
  32. * Intel 6th Gen Core i3/i5/i7 (Skylake)
  33. * Intel 6th Gen Core i7/i9 (Skylake X)
  34.  
  35. It also offers to compile passing the 'native' option which, "selects the CPU
  36. to generate code for at compilation time by determining the processor type of
  37. the compiling machine. Using -march=native enables all instruction subsets
  38. supported by the local machine and will produce code optimized for the local
  39. machine under the constraints of the selected instruction set."[3]
  40.  
  41. MINOR NOTES
  42. This patch also changes 'atom' to 'bonnell' in accordance with the gcc v4.9
  43. changes. Note that upstream is using the deprecated 'match=atom' flags when I
  44. believe it should use the newer 'march=bonnell' flag for atom processors.[2]
  45.  
  46. It is not recommended to compile on Atom-CPUs with the 'native' option.[4] The
  47. recommendation is to use the 'atom' option instead.
  48.  
  49. BENEFITS
  50. Small but real speed increases are measurable using a make endpoint comparing
  51. a generic kernel to one built with one of the respective microarchs.
  52.  
  53. See the following experimental evidence supporting this statement:
  54. https://github.com/graysky2/kernel_gcc_patch
  55.  
  56. REQUIREMENTS
  57. linux version >=4.13
  58. gcc version >=4.9
  59.  
  60. ACKNOWLEDGMENTS
  61. This patch builds on the seminal work by Jeroen.[5]
  62.  
  63. REFERENCES
  64. 1. https://gcc.gnu.org/gcc-4.9/changes.html
  65. 2. https://bugzilla.kernel.org/show_bug.cgi?id=77461
  66. 3. https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html
  67. 4. https://github.com/graysky2/kernel_gcc_patch/issues/15
  68. 5. http://www.linuxforge.net/docs/linux/linux-gcc.php
  69.  
  70. --- a/arch/x86/include/asm/module.h 2018-01-28 16:20:33.000000000 -0500
  71. +++ b/arch/x86/include/asm/module.h 2018-03-10 06:42:38.688317317 -0500
  72. @@ -25,6 +25,26 @@ struct mod_arch_specific {
  73. #define MODULE_PROC_FAMILY "586MMX "
  74. #elif defined CONFIG_MCORE2
  75. #define MODULE_PROC_FAMILY "CORE2 "
  76. +#elif defined CONFIG_MNATIVE
  77. +#define MODULE_PROC_FAMILY "NATIVE "
  78. +#elif defined CONFIG_MNEHALEM
  79. +#define MODULE_PROC_FAMILY "NEHALEM "
  80. +#elif defined CONFIG_MWESTMERE
  81. +#define MODULE_PROC_FAMILY "WESTMERE "
  82. +#elif defined CONFIG_MSILVERMONT
  83. +#define MODULE_PROC_FAMILY "SILVERMONT "
  84. +#elif defined CONFIG_MSANDYBRIDGE
  85. +#define MODULE_PROC_FAMILY "SANDYBRIDGE "
  86. +#elif defined CONFIG_MIVYBRIDGE
  87. +#define MODULE_PROC_FAMILY "IVYBRIDGE "
  88. +#elif defined CONFIG_MHASWELL
  89. +#define MODULE_PROC_FAMILY "HASWELL "
  90. +#elif defined CONFIG_MBROADWELL
  91. +#define MODULE_PROC_FAMILY "BROADWELL "
  92. +#elif defined CONFIG_MSKYLAKE
  93. +#define MODULE_PROC_FAMILY "SKYLAKE "
  94. +#elif defined CONFIG_MSKYLAKE
  95. +#define MODULE_PROC_FAMILY "SKYLAKEX "
  96. #elif defined CONFIG_MATOM
  97. #define MODULE_PROC_FAMILY "ATOM "
  98. #elif defined CONFIG_M686
  99. @@ -43,6 +63,26 @@ struct mod_arch_specific {
  100. #define MODULE_PROC_FAMILY "K7 "
  101. #elif defined CONFIG_MK8
  102. #define MODULE_PROC_FAMILY "K8 "
  103. +#elif defined CONFIG_MK8SSE3
  104. +#define MODULE_PROC_FAMILY "K8SSE3 "
  105. +#elif defined CONFIG_MK10
  106. +#define MODULE_PROC_FAMILY "K10 "
  107. +#elif defined CONFIG_MBARCELONA
  108. +#define MODULE_PROC_FAMILY "BARCELONA "
  109. +#elif defined CONFIG_MBOBCAT
  110. +#define MODULE_PROC_FAMILY "BOBCAT "
  111. +#elif defined CONFIG_MBULLDOZER
  112. +#define MODULE_PROC_FAMILY "BULLDOZER "
  113. +#elif defined CONFIG_MPILEDRIVER
  114. +#define MODULE_PROC_FAMILY "PILEDRIVER "
  115. +#elif defined CONFIG_MSTEAMROLLER
  116. +#define MODULE_PROC_FAMILY "STEAMROLLER "
  117. +#elif defined CONFIG_MJAGUAR
  118. +#define MODULE_PROC_FAMILY "JAGUAR "
  119. +#elif defined CONFIG_MEXCAVATOR
  120. +#define MODULE_PROC_FAMILY "EXCAVATOR "
  121. +#elif defined CONFIG_MZEN
  122. +#define MODULE_PROC_FAMILY "ZEN "
  123. #elif defined CONFIG_MELAN
  124. #define MODULE_PROC_FAMILY "ELAN "
  125. #elif defined CONFIG_MCRUSOE
  126. --- a/arch/x86/Kconfig.cpu 2018-01-28 16:20:33.000000000 -0500
  127. +++ b/arch/x86/Kconfig.cpu 2018-03-10 06:45:50.244371799 -0500
  128. @@ -116,6 +116,7 @@ config MPENTIUMM
  129. config MPENTIUM4
  130. bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
  131. depends on X86_32
  132. + select X86_P6_NOP
  133. ---help---
  134. Select this for Intel Pentium 4 chips. This includes the
  135. Pentium 4, Pentium D, P4-based Celeron and Xeon, and
  136. @@ -148,9 +149,8 @@ config MPENTIUM4
  137. -Paxville
  138. -Dempsey
  139.  
  140. -
  141. config MK6
  142. - bool "K6/K6-II/K6-III"
  143. + bool "AMD K6/K6-II/K6-III"
  144. depends on X86_32
  145. ---help---
  146. Select this for an AMD K6-family processor. Enables use of
  147. @@ -158,7 +158,7 @@ config MK6
  148. flags to GCC.
  149.  
  150. config MK7
  151. - bool "Athlon/Duron/K7"
  152. + bool "AMD Athlon/Duron/K7"
  153. depends on X86_32
  154. ---help---
  155. Select this for an AMD Athlon K7-family processor. Enables use of
  156. @@ -166,12 +166,83 @@ config MK7
  157. flags to GCC.
  158.  
  159. config MK8
  160. - bool "Opteron/Athlon64/Hammer/K8"
  161. + bool "AMD Opteron/Athlon64/Hammer/K8"
  162. ---help---
  163. Select this for an AMD Opteron or Athlon64 Hammer-family processor.
  164. Enables use of some extended instructions, and passes appropriate
  165. optimization flags to GCC.
  166.  
  167. +config MK8SSE3
  168. + bool "AMD Opteron/Athlon64/Hammer/K8 with SSE3"
  169. + ---help---
  170. + Select this for improved AMD Opteron or Athlon64 Hammer-family processors.
  171. + Enables use of some extended instructions, and passes appropriate
  172. + optimization flags to GCC.
  173. +
  174. +config MK10
  175. + bool "AMD 61xx/7x50/PhenomX3/X4/II/K10"
  176. + ---help---
  177. + Select this for an AMD 61xx Eight-Core Magny-Cours, Athlon X2 7x50,
  178. + Phenom X3/X4/II, Athlon II X2/X3/X4, or Turion II-family processor.
  179. + Enables use of some extended instructions, and passes appropriate
  180. + optimization flags to GCC.
  181. +
  182. +config MBARCELONA
  183. + bool "AMD Barcelona"
  184. + ---help---
  185. + Select this for AMD Family 10h Barcelona processors.
  186. +
  187. + Enables -march=barcelona
  188. +
  189. +config MBOBCAT
  190. + bool "AMD Bobcat"
  191. + ---help---
  192. + Select this for AMD Family 14h Bobcat processors.
  193. +
  194. + Enables -march=btver1
  195. +
  196. +config MJAGUAR
  197. + bool "AMD Jaguar"
  198. + ---help---
  199. + Select this for AMD Family 16h Jaguar processors.
  200. +
  201. + Enables -march=btver2
  202. +
  203. +config MBULLDOZER
  204. + bool "AMD Bulldozer"
  205. + ---help---
  206. + Select this for AMD Family 15h Bulldozer processors.
  207. +
  208. + Enables -march=bdver1
  209. +
  210. +config MPILEDRIVER
  211. + bool "AMD Piledriver"
  212. + ---help---
  213. + Select this for AMD Family 15h Piledriver processors.
  214. +
  215. + Enables -march=bdver2
  216. +
  217. +config MSTEAMROLLER
  218. + bool "AMD Steamroller"
  219. + ---help---
  220. + Select this for AMD Family 15h Steamroller processors.
  221. +
  222. + Enables -march=bdver3
  223. +
  224. +config MEXCAVATOR
  225. + bool "AMD Excavator"
  226. + ---help---
  227. + Select this for AMD Family 15h Excavator processors.
  228. +
  229. + Enables -march=bdver4
  230. +
  231. +config MZEN
  232. + bool "AMD Zen"
  233. + ---help---
  234. + Select this for AMD Family 17h Zen processors.
  235. +
  236. + Enables -march=znver1
  237. +
  238. config MCRUSOE
  239. bool "Crusoe"
  240. depends on X86_32
  241. @@ -253,6 +324,7 @@ config MVIAC7
  242.  
  243. config MPSC
  244. bool "Intel P4 / older Netburst based Xeon"
  245. + select X86_P6_NOP
  246. depends on X86_64
  247. ---help---
  248. Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
  249. @@ -262,8 +334,19 @@ config MPSC
  250. using the cpu family field
  251. in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
  252.  
  253. +config MATOM
  254. + bool "Intel Atom"
  255. + select X86_P6_NOP
  256. + ---help---
  257. +
  258. + Select this for the Intel Atom platform. Intel Atom CPUs have an
  259. + in-order pipelining architecture and thus can benefit from
  260. + accordingly optimized code. Use a recent GCC with specific Atom
  261. + support in order to fully benefit from selecting this option.
  262. +
  263. config MCORE2
  264. - bool "Core 2/newer Xeon"
  265. + bool "Intel Core 2"
  266. + select X86_P6_NOP
  267. ---help---
  268.  
  269. Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
  270. @@ -271,14 +354,88 @@ config MCORE2
  271. family in /proc/cpuinfo. Newer ones have 6 and older ones 15
  272. (not a typo)
  273.  
  274. -config MATOM
  275. - bool "Intel Atom"
  276. + Enables -march=core2
  277. +
  278. +config MNEHALEM
  279. + bool "Intel Nehalem"
  280. + select X86_P6_NOP
  281. ---help---
  282.  
  283. - Select this for the Intel Atom platform. Intel Atom CPUs have an
  284. - in-order pipelining architecture and thus can benefit from
  285. - accordingly optimized code. Use a recent GCC with specific Atom
  286. - support in order to fully benefit from selecting this option.
  287. + Select this for 1st Gen Core processors in the Nehalem family.
  288. +
  289. + Enables -march=nehalem
  290. +
  291. +config MWESTMERE
  292. + bool "Intel Westmere"
  293. + select X86_P6_NOP
  294. + ---help---
  295. +
  296. + Select this for the Intel Westmere formerly Nehalem-C family.
  297. +
  298. + Enables -march=westmere
  299. +
  300. +config MSILVERMONT
  301. + bool "Intel Silvermont"
  302. + select X86_P6_NOP
  303. + ---help---
  304. +
  305. + Select this for the Intel Silvermont platform.
  306. +
  307. + Enables -march=silvermont
  308. +
  309. +config MSANDYBRIDGE
  310. + bool "Intel Sandy Bridge"
  311. + select X86_P6_NOP
  312. + ---help---
  313. +
  314. + Select this for 2nd Gen Core processors in the Sandy Bridge family.
  315. +
  316. + Enables -march=sandybridge
  317. +
  318. +config MIVYBRIDGE
  319. + bool "Intel Ivy Bridge"
  320. + select X86_P6_NOP
  321. + ---help---
  322. +
  323. + Select this for 3rd Gen Core processors in the Ivy Bridge family.
  324. +
  325. + Enables -march=ivybridge
  326. +
  327. +config MHASWELL
  328. + bool "Intel Haswell"
  329. + select X86_P6_NOP
  330. + ---help---
  331. +
  332. + Select this for 4th Gen Core processors in the Haswell family.
  333. +
  334. + Enables -march=haswell
  335. +
  336. +config MBROADWELL
  337. + bool "Intel Broadwell"
  338. + select X86_P6_NOP
  339. + ---help---
  340. +
  341. + Select this for 5th Gen Core processors in the Broadwell family.
  342. +
  343. + Enables -march=broadwell
  344. +
  345. +config MSKYLAKE
  346. + bool "Intel Skylake"
  347. + select X86_P6_NOP
  348. + ---help---
  349. +
  350. + Select this for 6th Gen Core processors in the Skylake family.
  351. +
  352. + Enables -march=skylake
  353. +
  354. +config MSKYLAKEX
  355. + bool "Intel Skylake X"
  356. + select X86_P6_NOP
  357. + ---help---
  358. +
  359. + Select this for 6th Gen Core processors in the Skylake X family.
  360. +
  361. + Enables -march=skylake-avx512
  362.  
  363. config GENERIC_CPU
  364. bool "Generic-x86-64"
  365. @@ -287,6 +444,19 @@ config GENERIC_CPU
  366. Generic x86-64 CPU.
  367. Run equally well on all x86-64 CPUs.
  368.  
  369. +config MNATIVE
  370. + bool "Native optimizations autodetected by GCC"
  371. + ---help---
  372. +
  373. + GCC 4.2 and above support -march=native, which automatically detects
  374. + the optimum settings to use based on your processor. -march=native
  375. + also detects and applies additional settings beyond -march specific
  376. + to your CPU, (eg. -msse4). Unless you have a specific reason not to
  377. + (e.g. distcc cross-compiling), you should probably be using
  378. + -march=native rather than anything listed below.
  379. +
  380. + Enables -march=native
  381. +
  382. endchoice
  383.  
  384. config X86_GENERIC
  385. @@ -311,7 +481,7 @@ config X86_INTERNODE_CACHE_SHIFT
  386. config X86_L1_CACHE_SHIFT
  387. int
  388. default "7" if MPENTIUM4 || MPSC
  389. - default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
  390. + default "6" if MK7 || MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MJAGUAR || MPENTIUMM || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MNATIVE || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
  391. default "4" if MELAN || M486 || MGEODEGX1
  392. default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
  393.  
  394. @@ -342,35 +512,36 @@ config X86_ALIGNMENT_16
  395.  
  396. config X86_INTEL_USERCOPY
  397. def_bool y
  398. - depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
  399. + depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK8SSE3 || MK7 || MEFFICEON || MCORE2 || MK10 || MBARCELONA || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MNATIVE
  400.  
  401. config X86_USE_PPRO_CHECKSUM
  402. def_bool y
  403. - depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM
  404. + depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MK10 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MATOM || MNATIVE
  405.  
  406. config X86_USE_3DNOW
  407. def_bool y
  408. depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML
  409.  
  410. -#
  411. -# P6_NOPs are a relatively minor optimization that require a family >=
  412. -# 6 processor, except that it is broken on certain VIA chips.
  413. -# Furthermore, AMD chips prefer a totally different sequence of NOPs
  414. -# (which work on all CPUs). In addition, it looks like Virtual PC
  415. -# does not understand them.
  416. -#
  417. -# As a result, disallow these if we're not compiling for X86_64 (these
  418. -# NOPs do work on all x86-64 capable chips); the list of processors in
  419. -# the right-hand clause are the cores that benefit from this optimization.
  420. -#
  421. config X86_P6_NOP
  422. - def_bool y
  423. - depends on X86_64
  424. - depends on (MCORE2 || MPENTIUM4 || MPSC)
  425. + default n
  426. + bool "Support for P6_NOPs on Intel chips"
  427. + depends on (MCORE2 || MPENTIUM4 || MPSC || MATOM || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MNATIVE)
  428. + ---help---
  429. + P6_NOPs are a relatively minor optimization that require a family >=
  430. + 6 processor, except that it is broken on certain VIA chips.
  431. + Furthermore, AMD chips prefer a totally different sequence of NOPs
  432. + (which work on all CPUs). In addition, it looks like Virtual PC
  433. + does not understand them.
  434. +
  435. + As a result, disallow these if we're not compiling for X86_64 (these
  436. + NOPs do work on all x86-64 capable chips); the list of processors in
  437. + the right-hand clause are the cores that benefit from this optimization.
  438. +
  439. + Say Y if you have Intel CPU newer than Pentium Pro, N otherwise.
  440.  
  441. config X86_TSC
  442. def_bool y
  443. - depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64
  444. + depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MK8SSE3 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MNATIVE || MATOM) || X86_64
  445.  
  446. config X86_CMPXCHG64
  447. def_bool y
  448. @@ -380,7 +551,7 @@ config X86_CMPXCHG64
  449. # generates cmov.
  450. config X86_CMOV
  451. def_bool y
  452. - depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX)
  453. + depends on (MK8 || MK8SSE3 || MK10 || MBARCELONA || MBOBCAT || MBULLDOZER || MPILEDRIVER || MSTEAMROLLER || MEXCAVATOR || MZEN || MJAGUAR || MK7 || MCORE2 || MNEHALEM || MWESTMERE || MSILVERMONT || MSANDYBRIDGE || MIVYBRIDGE || MHASWELL || MBROADWELL || MSKYLAKE || MSKYLAKEX || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MNATIVE || MATOM || MGEODE_LX)
  454.  
  455. config X86_MINIMUM_CPU_FAMILY
  456. int
  457. --- a/arch/x86/Makefile 2018-01-28 16:20:33.000000000 -0500
  458. +++ b/arch/x86/Makefile 2018-03-10 06:47:00.284240139 -0500
  459. @@ -124,13 +124,42 @@ else
  460. KBUILD_CFLAGS += $(call cc-option,-mskip-rax-setup)
  461.  
  462. # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu)
  463. + cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native)
  464. cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8)
  465. + cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-mtune=k8)
  466. + cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10)
  467. + cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona)
  468. + cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1)
  469. + cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2)
  470. + cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1)
  471. + cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2)
  472. + cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3)
  473. + cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4)
  474. + cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1)
  475. cflags-$(CONFIG_MPSC) += $(call cc-option,-march=nocona)
  476.  
  477. cflags-$(CONFIG_MCORE2) += \
  478. - $(call cc-option,-march=core2,$(call cc-option,-mtune=generic))
  479. - cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom) \
  480. - $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))
  481. + $(call cc-option,-march=core2,$(call cc-option,-mtune=core2))
  482. + cflags-$(CONFIG_MNEHALEM) += \
  483. + $(call cc-option,-march=nehalem,$(call cc-option,-mtune=nehalem))
  484. + cflags-$(CONFIG_MWESTMERE) += \
  485. + $(call cc-option,-march=westmere,$(call cc-option,-mtune=westmere))
  486. + cflags-$(CONFIG_MSILVERMONT) += \
  487. + $(call cc-option,-march=silvermont,$(call cc-option,-mtune=silvermont))
  488. + cflags-$(CONFIG_MSANDYBRIDGE) += \
  489. + $(call cc-option,-march=sandybridge,$(call cc-option,-mtune=sandybridge))
  490. + cflags-$(CONFIG_MIVYBRIDGE) += \
  491. + $(call cc-option,-march=ivybridge,$(call cc-option,-mtune=ivybridge))
  492. + cflags-$(CONFIG_MHASWELL) += \
  493. + $(call cc-option,-march=haswell,$(call cc-option,-mtune=haswell))
  494. + cflags-$(CONFIG_MBROADWELL) += \
  495. + $(call cc-option,-march=broadwell,$(call cc-option,-mtune=broadwell))
  496. + cflags-$(CONFIG_MSKYLAKE) += \
  497. + $(call cc-option,-march=skylake,$(call cc-option,-mtune=skylake))
  498. + cflags-$(CONFIG_MSKYLAKEX) += \
  499. + $(call cc-option,-march=skylake-avx512,$(call cc-option,-mtune=skylake-avx512))
  500. + cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell) \
  501. + $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic))
  502. cflags-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=generic)
  503. KBUILD_CFLAGS += $(cflags-y)
  504.  
  505. --- a/arch/x86/Makefile_32.cpu 2018-01-28 16:20:33.000000000 -0500
  506. +++ b/arch/x86/Makefile_32.cpu 2018-03-10 06:47:46.025992644 -0500
  507. @@ -23,7 +23,18 @@ cflags-$(CONFIG_MK6) += -march=k6
  508. # Please note, that patches that add -march=athlon-xp and friends are pointless.
  509. # They make zero difference whatsosever to performance at this time.
  510. cflags-$(CONFIG_MK7) += -march=athlon
  511. +cflags-$(CONFIG_MNATIVE) += $(call cc-option,-march=native)
  512. cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8,-march=athlon)
  513. +cflags-$(CONFIG_MK8SSE3) += $(call cc-option,-march=k8-sse3,-march=athlon)
  514. +cflags-$(CONFIG_MK10) += $(call cc-option,-march=amdfam10,-march=athlon)
  515. +cflags-$(CONFIG_MBARCELONA) += $(call cc-option,-march=barcelona,-march=athlon)
  516. +cflags-$(CONFIG_MBOBCAT) += $(call cc-option,-march=btver1,-march=athlon)
  517. +cflags-$(CONFIG_MJAGUAR) += $(call cc-option,-march=btver2,-march=athlon)
  518. +cflags-$(CONFIG_MBULLDOZER) += $(call cc-option,-march=bdver1,-march=athlon)
  519. +cflags-$(CONFIG_MPILEDRIVER) += $(call cc-option,-march=bdver2,-march=athlon)
  520. +cflags-$(CONFIG_MSTEAMROLLER) += $(call cc-option,-march=bdver3,-march=athlon)
  521. +cflags-$(CONFIG_MEXCAVATOR) += $(call cc-option,-march=bdver4,-march=athlon)
  522. +cflags-$(CONFIG_MZEN) += $(call cc-option,-march=znver1,-march=athlon)
  523. cflags-$(CONFIG_MCRUSOE) += -march=i686 -falign-functions=0 -falign-jumps=0 -falign-loops=0
  524. cflags-$(CONFIG_MEFFICEON) += -march=i686 $(call tune,pentium3) -falign-functions=0 -falign-jumps=0 -falign-loops=0
  525. cflags-$(CONFIG_MWINCHIPC6) += $(call cc-option,-march=winchip-c6,-march=i586)
  526. @@ -32,8 +43,17 @@ cflags-$(CONFIG_MCYRIXIII) += $(call cc-
  527. cflags-$(CONFIG_MVIAC3_2) += $(call cc-option,-march=c3-2,-march=i686)
  528. cflags-$(CONFIG_MVIAC7) += -march=i686
  529. cflags-$(CONFIG_MCORE2) += -march=i686 $(call tune,core2)
  530. -cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom,$(call cc-option,-march=core2,-march=i686)) \
  531. - $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))
  532. +cflags-$(CONFIG_MNEHALEM) += -march=i686 $(call tune,nehalem)
  533. +cflags-$(CONFIG_MWESTMERE) += -march=i686 $(call tune,westmere)
  534. +cflags-$(CONFIG_MSILVERMONT) += -march=i686 $(call tune,silvermont)
  535. +cflags-$(CONFIG_MSANDYBRIDGE) += -march=i686 $(call tune,sandybridge)
  536. +cflags-$(CONFIG_MIVYBRIDGE) += -march=i686 $(call tune,ivybridge)
  537. +cflags-$(CONFIG_MHASWELL) += -march=i686 $(call tune,haswell)
  538. +cflags-$(CONFIG_MBROADWELL) += -march=i686 $(call tune,broadwell)
  539. +cflags-$(CONFIG_MSKYLAKE) += -march=i686 $(call tune,skylake)
  540. +cflags-$(CONFIG_MSKYLAKEX) += -march=i686 $(call tune,skylake-avx512)
  541. +cflags-$(CONFIG_MATOM) += $(call cc-option,-march=bonnell,$(call cc-option,-march=core2,-march=i686)) \
  542. + $(call cc-option,-mtune=bonnell,$(call cc-option,-mtune=generic))
  543.  
  544. # AMD Elan support
  545. cflags-$(CONFIG_MELAN) += -march=i486
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