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STM32F4_Clock_Config_Working

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Oct 12th, 2017
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  1. #include "clockConfig.h"
  2. /**************************************************************************/
  3. void SystemClock_Config(void)
  4. {
  5.   uint32_t temp;
  6.   /***************************************************************************/
  7.   /* Enable Power Control clock */
  8.   RCC->APB1ENR |= 0x10000000;   // Enable PWREN bit (page - 183 of RM)
  9.   /**************************************************************************/
  10.  
  11.   /* The voltage scaling allows optimizing the power consumption when the device is
  12.      clocked below the maximum system frequency, to update the voltage scaling value
  13.      regarding system frequency refer to product datasheet.  */
  14.   PWR->CR |= 0x00004000;    //VOS bit = 01 (page - 145 or RM)
  15.   /**************************************************************************/
  16. #ifdef USE_HSE
  17.   //RCC->CR &= ~0x00000001; // HSI OFF, not guranteed, but does not matter, may be slight increase in current
  18.   RCC->CR |= 0x00010000;    // HSE ON
  19.   while((RCC->CR & 0x00020000) == 0);   // Wait till HSE is ready
  20.  
  21.   // Set PLL
  22.   temp = 0x00400000;    // PLL source is HSE (PLLSRC bit is set to one)
  23. #endif
  24.   /**************************************************************************/
  25. #ifdef USE_HSI
  26.   RCC->CR |= 0x00000001;    // HSI ON
  27.   //RCC->CR &= ~0x00010000; // HSE OFF, not guranted, but does not matter, may be slight increase in current
  28.   while((RCC->CR & 0x00000002) == 0);   // Wait till HSI is ready
  29.  
  30.   // Set PLL
  31.   temp = 0x00000000;    // PLL source is HSI (PLLSRC bit is cleared to zero)
  32. #endif
  33.   /**************************************************************************/
  34.   temp |= (uint32_t)PLL_M;
  35.   temp |= ((uint32_t)PLL_N << 6);
  36.   temp |= ((uint32_t)PLL_P << 16);
  37.   temp |= ((uint32_t)PLL_Q << 24);
  38.   RCC->PLLCFGR = temp;
  39.   /**************************************************************************/
  40.   // Select PLLCLK as SYSCLK, APB2, APB1 and AHB
  41.   temp = RCC->CFGR;
  42.   temp |= ((uint32_t)AHB_PRESCALAR << 4);
  43.   temp |= ((uint32_t)APB1_PRESCALAR << 10);
  44.   temp |= ((uint32_t)APB2_PRESCALAR << 13);
  45.   temp |= 0x00000002;           // Select PLL as SYSCLK
  46.   RCC->CFGR = temp;
  47.   /**************************************************************************/
  48.   FLASH->ACR |= 0x00000005; // FLASH_LATENCY_5
  49.   /**************************************************************************/
  50.   // Now, switch ON the PLL
  51.   RCC->CR |= 0x01000000;    // PLL ON
  52.   while((RCC->CR & 0x02000000) == 0);   // Wait till PLL is ready
  53.   /**************************************************************************/
  54.   // wait till PLL is really used as SYSCLK
  55.   while((RCC->CFGR & 0x00000008) == 0); // Make sure SWS = 0b10 = PLL is really selected
  56.   /**************************************************************************/
  57.    /* STM32F405x/407x/415x/417x Revision Z devices: prefetch is supported  */
  58.   volatile uint32_t idNumber = DBGMCU->IDCODE;
  59.   idNumber = idNumber >> 16;
  60.   /**************************************************************************/
  61.   /* Enable the Flash prefetch */
  62.   if(idNumber == 0x1001)
  63.   {
  64.       FLASH->ACR |= 0x00000100;
  65.   }
  66. }
  67. /**************************************************************************/
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