Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- #include "clockConfig.h"
- /**************************************************************************/
- void SystemClock_Config(void)
- {
- uint32_t temp;
- /***************************************************************************/
- /* Enable Power Control clock */
- RCC->APB1ENR |= 0x10000000; // Enable PWREN bit (page - 183 of RM)
- /**************************************************************************/
- /* The voltage scaling allows optimizing the power consumption when the device is
- clocked below the maximum system frequency, to update the voltage scaling value
- regarding system frequency refer to product datasheet. */
- PWR->CR |= 0x00004000; //VOS bit = 01 (page - 145 or RM)
- /**************************************************************************/
- #ifdef USE_HSE
- //RCC->CR &= ~0x00000001; // HSI OFF, not guranteed, but does not matter, may be slight increase in current
- RCC->CR |= 0x00010000; // HSE ON
- while((RCC->CR & 0x00020000) == 0); // Wait till HSE is ready
- // Set PLL
- temp = 0x00400000; // PLL source is HSE (PLLSRC bit is set to one)
- #endif
- /**************************************************************************/
- #ifdef USE_HSI
- RCC->CR |= 0x00000001; // HSI ON
- //RCC->CR &= ~0x00010000; // HSE OFF, not guranted, but does not matter, may be slight increase in current
- while((RCC->CR & 0x00000002) == 0); // Wait till HSI is ready
- // Set PLL
- temp = 0x00000000; // PLL source is HSI (PLLSRC bit is cleared to zero)
- #endif
- /**************************************************************************/
- temp |= (uint32_t)PLL_M;
- temp |= ((uint32_t)PLL_N << 6);
- temp |= ((uint32_t)PLL_P << 16);
- temp |= ((uint32_t)PLL_Q << 24);
- RCC->PLLCFGR = temp;
- /**************************************************************************/
- // Select PLLCLK as SYSCLK, APB2, APB1 and AHB
- temp = RCC->CFGR;
- temp |= ((uint32_t)AHB_PRESCALAR << 4);
- temp |= ((uint32_t)APB1_PRESCALAR << 10);
- temp |= ((uint32_t)APB2_PRESCALAR << 13);
- temp |= 0x00000002; // Select PLL as SYSCLK
- RCC->CFGR = temp;
- /**************************************************************************/
- FLASH->ACR |= 0x00000005; // FLASH_LATENCY_5
- /**************************************************************************/
- // Now, switch ON the PLL
- RCC->CR |= 0x01000000; // PLL ON
- while((RCC->CR & 0x02000000) == 0); // Wait till PLL is ready
- /**************************************************************************/
- // wait till PLL is really used as SYSCLK
- while((RCC->CFGR & 0x00000008) == 0); // Make sure SWS = 0b10 = PLL is really selected
- /**************************************************************************/
- /* STM32F405x/407x/415x/417x Revision Z devices: prefetch is supported */
- volatile uint32_t idNumber = DBGMCU->IDCODE;
- idNumber = idNumber >> 16;
- /**************************************************************************/
- /* Enable the Flash prefetch */
- if(idNumber == 0x1001)
- {
- FLASH->ACR |= 0x00000100;
- }
- }
- /**************************************************************************/
Add Comment
Please, Sign In to add comment