Gray_test

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-- Company:
-- Engineer:
--
-- Create Date:   12:21:48 03/10/2019
-- Design Name:
-- Module Name:   C:/ZapiskiStudenckie/Gray/Gray_test.vhd
-- Project Name:  Gray
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Gray_kod
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY Gray_test IS
END Gray_test;

ARCHITECTURE behavior OF Gray_test IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Gray_kod
    PORT(
         CLK : IN  std_logic;
         RST : IN  std_logic;
         LED_0 : OUT  std_logic;
         LED_1 : OUT  std_logic);
    END COMPONENT;


   --Inputs
   signal CLK : std_logic := '0';
   signal RST : std_logic := '0';

    --Outputs
   signal LED_0 : std_logic;
   signal LED_1 : std_logic;


BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: Gray_kod PORT MAP (
          CLK => CLK,
          RST => RST,
          LED_0 => LED_0,
          LED_1 => LED_1
        );



   stim_proc: process
   begin

            CLK <= '1';
            wait for 10 ns;
            CLK <= '0';
            wait for 10 ns;
            CLK <= '1';
            wait for 4 ns;
            RST <= '1';
            wait for 2 ns;
            RST <= '0';
            wait for 4 ns;
            CLK <= '0';
            wait for 10 ns;
            CLK <= '1';
            wait for 10 ns;
            CLK <= '0';
            wait for 10 ns;
            CLK <= '1';
            wait for 10 ns;
            CLK <= '0';
            wait for 10 ns;
            CLK <= '1';
            wait for 10 ns;
            CLK <= '0';
            wait for 10 ns;
            CLK <= '1';
            wait for 10 ns;
            CLK <= '0';
            wait for 10 ns;
            CLK <= '1';
            wait for 10 ns;
            CLK <= '0';
            wait;
   end process;

END;