library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use work.JPU16_Pack.all;

entity SistemaPrincipal is
	Generic( AnchoBus: integer := 16);
    Port ( clk : in  STD_LOGIC;
			  SalPort: out STD_LOGIC_VECTOR(AnchoBus-1 downto 0));
end SistemaPrincipal;

architecture Behavioral of SistemaPrincipal is

	signal BusOut: STD_LOGIC_vECTOR(AnchoBus-1 downto 0);
	signal SalPortReg: STD_LOGIC_vECTOR(AnchoBus-1 downto 0);
	signal WE:		 STD_LOGIC;
	signal TimerPort0:STD_LOGIC_VECTOR(AnchoBus-1 downto 0);
	signal IO_Addr: STD_LOGIC_VECTOR(AnchoBus-1 downto 0);
	signal IO_RD: STD_LOGIC;

	component STimer is
	Port(
			SysClk:  in	STD_LOGIC;
			IO_Addr: in STD_LOGIC_VECTOR( AnchoBus-1 downto 0);
			IO_Dout: in STD_LOGIC_VECTOR( AnchoBus-1 downto 0);
			IO_Din: out STD_LOGIC_VECTOR( AnchoBus-1 downto 0);
			IO_RD: 	in STD_LOGIC;
			IO_WE: 	in STD_LOGIC
	);
	end component;
begin

	Timer0: STimer
	Port map(
		SysClk => clk,
		IO_Addr => IO_Addr,
		IO_Dout => BusOut,
		IO_Din => TimerPort0,
		IO_RD => IO_RD,
		IO_WE => WE
	);

	CPU1: 	JPU16
	generic map(nInputPorts => 2
					)
	Port map(
			SysClk => clk,
			SysHold => '0',
			Int => '0',
			Reset => '0',
			IO_Addr => IO_Addr,
			IO_Dout => BusOut,
			IO_WR => WE,
			IO_RD => IO_RD,
			IO_Din(0) => (others => '0'),
			IO_Din(1) => TimerPort0
	);

SalPortReg <= BusOut when WE = '1' and rising_edge(clk) else SalPortReg;
SalPort <= SalPortReg;

end Behavioral;