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-- Company:
-- Engineer:
--
-- Create Date: 11/20/2019 03:48:28 PM
-- Design Name:
-- Module Name: ex1 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity ex1 is
  Port (i: IN std_logic;
reset, clock:IN std_logic;
O: OUT std_logic );
end ex1;

architecture Behavioral of ex1 is
type stare is (s0, s1, s2, s3, s4, s5, s6);
signal pr_state, nx_state: stare;

begin

PROCESS (reset, clock)
BEGIN
IF (reset='1') THEN
pr_state <= s0;
ELSIF (rising_edge(clock)) THEN
pr_state <= nx_state;
END IF;
END PROCESS;

PROCESS (i, pr_state)
BEGIN
CASE pr_state IS
    WHEN s0 =>
        IF (i = '0') then
            nx_state <= s1;
            O <= '1';
        elsif (i = '1') then
             nx_state <= s2;
             O <= '0';
       end if;
     WHEN s1 =>
           IF (i = '0') then
               nx_state <= s3;
               O <= '1';
           elsif (i = '1') then
                nx_state <= s4;
                O <= '0';
          end if;
    WHEN s2 =>
              IF (i = '0') then
                  nx_state <= s4;
                  O <= '0';
              elsif (i = '1') then
                   nx_state <= s4;
                   O <= '1';
             end if;

    WHEN s3 =>
      IF (i = '0') then
          nx_state <= s5;
          O <= '0';
      elsif (i = '1') then
           nx_state <= s5;
           O <= '1';
     end if;
    WHEN s4 =>
               IF (i = '0') then
                   nx_state <= s5;
                   O <= '1';
               elsif (i = '1') then
                    nx_state <= s6;
                    O <= '0';
              end if;
        WHEN s5 =>
                  IF (i = '0') then
                      nx_state <= s0;
                      O <= '0';
                  elsif (i = '1') then
                       nx_state <= s0;
                       O <= '1';
                 end if;

        WHEN s6 =>
                     IF (i = '0') then
                         nx_state <= s0;
                         O <= '1';
                    end if;
    end case;
  end process;
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_ex1 is
end tb_ex1;
architecture arc of tb_ex1 is
component ex1 is
port (i: IN std_logic;
reset, clock:IN std_logic;
O: OUT std_logic );
end component;
signal tb_input:  std_logic;
signal tb_rst:  std_logic;
signal tb_clk:  std_logic;
signal tb_0:  std_logic;

begin
ex1_i: ex1 port map (tb_input,tb_rst,tb_clk,tb_0);


tb_rst<='0','1' after 17 ns;
tb_clk<='0','1' after 5 ns, '0' after 10 ns;
tb_input <='1', '0' after 20 ns;

end;