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Dec 11th, 2017
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  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_ARITH.ALL;
  4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5.  
  6. entity Practica5 is
  7. Port ( G3 : in STD_LOGIC;
  8. G2 : in STD_LOGIC;
  9. G1 : in STD_LOGIC;
  10. G0 : in STD_LOGIC;
  11. P : out STD_LOGIC;
  12. S : out STD_LOGIC;
  13. T : out STD_LOGIC;
  14. C : out STD_LOGIC);
  15. end Practica5;
  16.  
  17. architecture Entorno of Practica5 is
  18.  
  19. signal entrada: std_logic_vector (3 downto 0);
  20.  
  21. begin
  22.  
  23. entrada <= G3 & G2 & G1 & G0;
  24.  
  25. P <= '1' when entrada = ("0000" or "0001" or "0011" or "0010") else
  26. '0';
  27.  
  28. with entrada select
  29. S <= '1' when "0110",
  30. '1' when "0111",
  31. '1' when "0101",
  32. '1' when "0100",
  33. '0' when others;
  34.  
  35. process(entrada)
  36. begin
  37. if entrada = ("1100" or "1101" or "1111" or "1110") then T <= '1';
  38. else T <= '0'; end if;
  39. end process;
  40.  
  41. process(entrada)
  42. begin
  43. case entrada is
  44. when "1010" => C <= '1';
  45. when "1011" => C <= '1';
  46. when "1001" => C <= '1';
  47. when "1000" => C <= '1';
  48. when others => C <= '0';
  49. end case;
  50. end process;
  51.  
  52. end Entorno;
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