Advertisement
Not a member of Pastebin yet?
Sign Up,
it unlocks many cool features!
- library IEEE;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_ARITH.ALL;
- use IEEE.STD_LOGIC_UNSIGNED.ALL;
- entity Practica5 is
- Port ( G3 : in STD_LOGIC;
- G2 : in STD_LOGIC;
- G1 : in STD_LOGIC;
- G0 : in STD_LOGIC;
- P : out STD_LOGIC;
- S : out STD_LOGIC;
- T : out STD_LOGIC;
- C : out STD_LOGIC);
- end Practica5;
- architecture Entorno of Practica5 is
- signal entrada: std_logic_vector (3 downto 0);
- begin
- entrada <= G3 & G2 & G1 & G0;
- P <= '1' when entrada = ("0000" or "0001" or "0011" or "0010") else
- '0';
- with entrada select
- S <= '1' when "0110",
- '1' when "0111",
- '1' when "0101",
- '1' when "0100",
- '0' when others;
- process(entrada)
- begin
- if entrada = ("1100" or "1101" or "1111" or "1110") then T <= '1';
- else T <= '0'; end if;
- end process;
- process(entrada)
- begin
- case entrada is
- when "1010" => C <= '1';
- when "1011" => C <= '1';
- when "1001" => C <= '1';
- when "1000" => C <= '1';
- when others => C <= '0';
- end case;
- end process;
- end Entorno;
Advertisement
Add Comment
Please, Sign In to add comment
Advertisement