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  1. library ieee;
  2. Use ieee.std_logic_1164.all;
  3.  
  4. entity lab3 is
  5.   port (SW: IN std_logic_vector(2 downto 0);
  6.         HEX7: OUT std_logic_vector(6 downto 0));
  7. END lab3;
  8.  
  9. architecture a of lab3 is
  10.  
  11.   signal c: std_logic_vector(2 downto 0);
  12.  
  13. begin
  14.   c <= SW(2 downto 0);
  15.   HEX7 <= "0001001" WHEN c="000" ELSE
  16.           "0000110" WHEN c="001" ELSE
  17.           "1000111" WHEN c="010" ELSE
  18.           "1000000" WHEN c="011" ELSE
  19.           "1111111" ;
  20. end a ; -lab3
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