//////////////////////////////////////////////////////////////////////////////////
// Data pattern injector for reducing edges rate
//////////////////////////////////////////////////////////////////////////////////

module restreamer(clk, reset, in, out);

input clk;              //Counter clock, must be 3*input data clock
input reset;            //Reset input active high
input wire in;    //Input data
output logic [3:0] out;       //Output data

logic [2:0] data_in_counter;

logic [6:0] data_temp;
logic [6:0] data;


//////////////////////////////////////////////////////////////////////////////////
always @ (posedge clk) begin
    data_temp <= {data_temp[5:0], in};
        if(data_in_counter == 3) begin
            data <= data_temp;
            data_in_counter <= 3'b0;
        end else begin
            data_in_counter <= data_in_counter + 1'b1;
        end
end

restreamer_retransmiter retrans0(
.clk(clk),
.reset(1'b0),
.data(data[3:0]),
.out(out[0]),
.data_in_counter(data_in_counter)
);

restreamer_retransmiter retrans1(
.clk(clk),
.reset(1'b0),
.data(data[4:1]),
.out(out[1]),
.data_in_counter(data_in_counter)
);

restreamer_retransmiter retrans2(
.clk(clk),
.reset(1'b0),
.data(data[5:2]),
.out(out[2]),
.data_in_counter(data_in_counter)
);

restreamer_retransmiter retrans3(
.clk(clk),
.reset(1'b0),
.data(data[6:3]),
.out(out[3]),
.data_in_counter(data_in_counter)
);

endmodule