library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hex_1sec is
port (
		clock_50 : in  BIT;
		LEDR_9 	: out 	BIT;
		display0	: OUT	STD_LOGIC_VECTOR(0 TO 6);
		display1	: OUT	STD_LOGIC_VECTOR(0 TO 6);
		display2	: OUT	STD_LOGIC_VECTOR(0 TO 6);
		display3	: OUT	STD_LOGIC_VECTOR(0 TO 6);
		display4	: OUT	STD_LOGIC_VECTOR(0 TO 6);
		display5	: OUT	STD_LOGIC_VECTOR(0 TO 6)
		);

end hex_1sec;

ARCHITECTURE behavior of hex_1sec is

component hex7seg is
port (
		hex		: IN	STD_LOGIC_VECTOR(3 DOWNTO 0);
		display	: OUT	STD_LOGIC_VECTOR(0 TO 6)
		);
end component;

signal trrr: 		integer 	:=0;
signal tik_tok:	bit	 	:='0';
signal tmp:			integer:=0;
signal ogranicznik: integer :=50000000;
signal war_0: STD_LOGIC_VECTOR (3 DOWNTO 0);
signal tik_0: integer:=0;


begin

	process (CLOCK_50)
		begin
			if (clock_50'event AND clock_50='1') then
				trrr <= trrr + 1;
			end if;
			if (trrr>ogranicznik) then
				trrr<=0;
				tmp<=tmp+1;
				if (tmp=1) then tmp<=0; end if;
				if (tik_tok='1') then tik_tok<='0';
				elsif(tik_tok='0') then tik_tok<='1';
				end if;
			end if;
	end process;

	process (tik_tok, clock_50)
		begin
			if (tik_tok='1') then ledr_9 <='0';
			elsif (tik_tok='0') then ledr_9 <='1';

			end if;
	end process;


		process (tik_tok, clock_50)
		begin
		if (tmp=1) then
				if (war_0="0000") then war_0<="0001";
				elsif (war_0="0001") then war_0<="0010";
				elsif (war_0="0010") then war_0<="0011";
				elsif (war_0="0011") then war_0<="1111";
				elsif (war_0="1111") then
					if (tik_0=5) then tik_0<=0;
					war_0<="0000";
				 	end if;
					tik_0<=tik_0+1;
				end if;
		end if;
		end process;


HEX_5_d: hex7seg port map ("0001",display5);
HEX_4_d: hex7seg port map ("0010",display4);
HEX_3_d: hex7seg port map ("0011",display3);
HEX_2_d: hex7seg port map ("1111",display2);
HEX_1_d: hex7seg port map ("1111",display1);
HEX_0_d: hex7seg port map (war_0,display0);


end behavior;