library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity SIMPLE_SRAM_CONTROLLER is

    port
    (
            CLK     :   in  std_logic;
            RESET       :   in  std_logic:='1';
            RnW     :   in std_logic:='1';
            ADDR    :   in unsigned(15 downto 0);
            DATA_IN :   in std_logic_vector(7 downto 0):="00000000";
            DATA_OUT    :   OUT std_logic_vector(7 downto 0) := "ZZZZZZZZ";
            DATA_BUS    :   INOUT   std_logic_vector(7 downto 0) :="ZZZZZZZZ";
            SRAM_ADDR:  OUT std_logic_vector(16 downto 0) := "00000000000000000";
            SRAM_DATA:  INOUT   std_logic_vector(7 downto 0) :="ZZZZZZZZ";
            SRAM_REGISTER   :   BUFFER std_logic_vector(7 downto 0):="00000000";
            SRAM_CS :   BUFFER std_logic:='1'
    );

end entity;

architecture behavioral of SIMPLE_SRAM_CONTROLLER is
signal CACHE    :   std_logic_vector(7 downto 0);

begin
SRAM_ADDR(13 downto 0) <= std_logic_vector(ADDR(13 downto 0));
SRAM_ADDR(16 downto 14) <= SRAM_REGISTER(2 downto 0);


--      manage_cache:process(CLK)
--      begin
--      DATA_BUS <= "ZZZZZZZZ";
--      if RnW = '0' then
--          CACHE <= DATA_BUS;
--      else
--          DATA_BUS <= CACHE;
--      end if;
--      end process;
--
--
--      register_setup:process(RESET,ADDR,RnW)
--      begin
--      if RESET = '0' then
--          SRAM_REGISTER <= "00000000";
--      else
--          if to_integer(ADDR(15 downto 0)) = 16#CE00# then
--              if RnW = '0' then
--                  SRAM_REGISTER <= CACHE;
--              else
--                  --SRAM_REGISTER <= "ZZZZZZZZ";
--                  CACHE <= SRAM_REGISTER;
--              end if;
--          end if;
--      end if;
--      end process;




decode:process(RESET,CLK)
begin

--wait until CLK = '1';
DATA_BUS <= "ZZZZZZZZ";
if RESET = '0' then
    SRAM_CS <= '1';
    SRAM_REGISTER<="00000000";
else
    if to_integer(ADDR(15 downto 0)) = 16#CE00# then
        if RnW = '0' then
            --SRAM_REGISTER <= DATA_BUS;
            SRAM_REGISTER <= DATA_BUS;
        else
            SRAM_REGISTER <= "ZZZZZZZZ";
            DATA_BUS <= SRAM_REGISTER;
        end if;
    else
        if to_integer(ADDR(15 downto 12)) >= 16#8# AND to_integer(ADDR(15 downto 12)) <= 16#B# then
            SRAM_CS <= '0';

            if RnW = '0' then
                DATA_BUS <= "ZZZZZZZZ";
                SRAM_DATA <= DATA_BUS;
            else
                SRAM_DATA <= "ZZZZZZZZ";
                DATA_BUS <= SRAM_DATA;
            end if;
        else
            SRAM_CS <= '1';
            SRAM_DATA <= "ZZZZZZZZ";
        end if;
    end if;
    --wait until CLK = '1';
    SRAM_CS <= '1';
    DATA_BUS <= "ZZZZZZZZ";
    --SRAM_REGISTER <= CACHE;
end if;

end process;
--
--      SRAM_TRANS:process(RESET,ADDR)
--      begin
--      if RESET = '0' then
--          --CS <= '1';
--      else
--          if RnW = '1' then
--              SRAM_DATA <= "ZZZZZZZZ";
--              DATA_OUT <= SRAM_DATA;
--          else
--              SRAM_DATA <= DATA_IN;
--          end if;
--      end if;
--      end process;

end behavioral;