Eat shit SE204

//-----------------------------------------------------------------
// Wishbone BlockRAM
//-----------------------------------------------------------------
//
// Le paramètre mem_adr_width doit permettre de déterminer le nombre
// de mots de la mémoire : (2048 pour mem_adr_width=11)

module wb_bram #(parameter mem_adr_width = 11) (
    // Wishbone interface
    wshb_if.slave wb_s
    );
    // a vous de jouer a partir d'ici
    logic [3:0][7:0] RAM[2 ** mem_adr_width - 1:0];

    // Synchrone burst indicator
    logic in_burst;
    // Combinatorial burst indicator
    wire in_real_time_burst;
    assign in_real_time_burst = wb_s.cti == 3'b010;

    wire [mem_adr_width - 1:0] relevant_addr;
    logic [mem_adr_width - 1:0] burst_next_addr;
    assign relevant_addr = in_burst ? burst_next_addr : wb_s.adr[mem_adr_width + 1:2];

    assign wb_s.rty = 1'b0;
    assign wb_s.err = 1'b0;

    logic opDone;
    assign wb_s.ack = wb_s.we ? wb_s.stb : opDone;

    always_ff @(posedge wb_s.clk or posedge wb_s.rst)
        if(wb_s.rst)
            opDone <= 1'b0;
        else
        begin
            burst_next_addr <= relevant_addr + (in_real_time_burst && wb_s.stb);
            in_burst <= in_real_time_burst;
            opDone <= in_real_time_burst || (!wb_s.we && wb_s.stb && !opDone);
        end

    always_ff @(posedge wb_s.clk)
        if(wb_s.stb)
        // Handle wishbone
        begin
            if(wb_s.we)
            // Write mode
            begin
                if(wb_s.sel[0])
                    RAM[relevant_addr][0] <= wb_s.dat_ms[7:0];
                if(wb_s.sel[1])
                    RAM[relevant_addr][1] <= wb_s.dat_ms[15:8];
                if(wb_s.sel[2])
                    RAM[relevant_addr][2] <= wb_s.dat_ms[23:16];
                if(wb_s.sel[3])
                    RAM[relevant_addr][3] <= wb_s.dat_ms[31:24];
            end
            wb_s.dat_sm <= RAM[relevant_addr];
        end

endmodule