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- library ieee;
- use ieee.std_logic_1164.all;
- use ieee.numeric_std.all;
- entity tb_top is
- end entity;
- architecture arch of tb_top is
- signal clk, rst, start : std_logic;
- signal ir : std_logic_vector(4 downto 0);
- signal an : std_logic_vector(3 downto 0);
- signal sseg : std_logic_vector(7 downto 0);
- begin
- dut:top_fib port map(clk,rst, start, ir, an, sseg);
- process
- begin
- clk <= '0';
- wait for 15 ns;
- clk <= '1';
- wait for 15 ns;
- end process;
- process
- begin
- rst <= '1';
- wait for 20 ns;
- rst <= '0';
- wait;
- end process;
- process
- begin
- start <= '1';
- wait for 50 ns;
- start <= '0';
- wait;
- end process;
- ir <= "01101"; -- o termo de número 13 na sequencia de Fibonacci, = 55
- end arch;
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