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tb_top

DomMisterSoja Apr 12th, 2018 21 Never
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  1. library ieee;
  2. use ieee.std_logic_1164.all;
  3. use ieee.numeric_std.all;
  4.  
  5. entity tb_top is
  6. end entity;
  7.  
  8. architecture arch of tb_top is
  9.   signal clk, rst, start : std_logic;
  10.   signal ir : std_logic_vector(4 downto 0);
  11.   signal an : std_logic_vector(3 downto 0);
  12.   signal sseg : std_logic_vector(7 downto 0);
  13.  
  14.   begin
  15.  
  16.     dut:top_fib port map(clk,rst, start, ir, an, sseg);
  17.                          
  18.   process
  19.       begin
  20.         clk <= '0';
  21.         wait for 15 ns;
  22.         clk <= '1';
  23.         wait for 15 ns;
  24.     end process;
  25.  
  26.    process
  27.       begin
  28.         rst <= '1';
  29.         wait for 20 ns;
  30.         rst <= '0';
  31.         wait;
  32.     end process;
  33.  
  34.    process
  35.       begin
  36.         start <= '1';
  37.         wait for 50 ns;
  38.         start <= '0';
  39.         wait;
  40.     end process;
  41.  
  42.   ir <= "01101";  -- o termo de nĂºmero 13 na sequencia de Fibonacci, = 55
  43.  
  44. end arch;
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