interface_toplevel.sv

// This file is weird, code wouldn't compile unless we passed signals through here first...
// This is basically an intermediate layer between testbench and the avalon_aes_interface.
// Why do we need it? Idk, probably some hierarchial issue, but all im doing here is passing signals
// from the testbench into here, which go straight to the avalon_aes_interface without being changed lmao.

module interface_toplevel  (
    // Avalon Clock Input
    input logic CLK,

    // Avalon Reset Input
    input logic RESET,

    // Avalon-MM Slave Signals
    input  logic AVL_READ,                  // Avalon-MM Read
    input  logic AVL_WRITE,                 // Avalon-MM Write
    input  logic AVL_CS,                        // Avalon-MM Chip Select
    input  logic [3:0] AVL_BYTE_EN,     // Avalon-MM Byte Enable
    input  logic [3:0] AVL_ADDR,            // Avalon-MM Address
    input  logic [31:0] AVL_WRITEDATA,  // Avalon-MM Write Data
    output logic [31:0] AVL_READDATA,   // Avalon-MM Read Data

    // Exported Conduit
    output logic [31:0] EXPORT_DATA     // Exported Conduit Signal to LEDs
                                    );
    avalon_aes_interface interfascist(.*);
endmodule