library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FSM_String is
    Port ( Clk : in  STD_LOGIC;
           Reset : in  STD_LOGIC;
           LCD_Busy : in  STD_LOGIC;
           LCD_WE : out  STD_LOGIC;
           LCD_DnI : out  STD_LOGIC;
           LCD_DI : out  STD_LOGIC_VECTOR (7 downto 0));
end FSM_String;

architecture RTL of FSM_String is

  -- FSM
  type state_type is (
    sReset,
    sBusyWait,
    sWE,
    sLoop
    );
  signal State, nextState : state_type;

  -- String to print
  type t_data is array (natural range <>) of std_logic_vector(7 downto 0);

  type t_sel is array (natural range <>) of std_logic;


  constant data_size : POSITIVE := 6;
  constant data : t_data ( 0 to data_size - 1 ) := ( x"45", x"41",  x"42", x"C1",  x"43",  x"34");
  constant sel  : t_sel ( 0 to data_size - 1 )  := (   '0',   '1',    '1',   '0',    '1',    '1');

  -- Character index
  signal cntIdx : integer range 0 to data_size ;

begin

  -- Character index
  process ( Clk )
  begin
    if rising_edge( Clk ) then
      if State = sReset then
        cntIdx <= 0;
      elsif State = sWE then
        cntIdx <= cntIdx + 1;
      end if;
    end if;
  end process;

  -- FSM
    process ( Clk )
  begin
    if rising_edge( Clk ) then
      if Reset = '1' then
        State <= sReset;
      else
        State <= nextState;
      end if;
    end if;
  end process;
    process( State, LCD_Busy, cntIdx)
  begin
    nextState <= State;   -- default is to stay in current State

    case State is

      when sReset =>
        nextState <= sBusyWait;

      when sBusyWait =>
        if LCD_Busy = '0' then
          nextState <= sWE;
        end if;

      when sWE =>   -- WE pulse
        nextState <= sLoop;

      when sLoop =>
        if cntIdx /= data_size then
          nextState <= sBusyWait;
        end if;   -- else null; => stay in sLoop till Reset

    end case;
  end process;


  LCD_WE  <= '1' when State = sWE else '0';
  -- Outputs

  process (Clk)

   begin

      if sel(cntIdx) = '0' then

      LCD_DnI <= '0';

      else

      LCD_DnI <= '1';

      end if;



      LCD_DI <= data(cntIdx);
   end process;


end RTL;