library ieee;
USE ieee.std_logic_1164.all;
ENTITY adder IS PORT (
     a, b: IN std_logic_vector (3 DOWNTO 0);
     sum: OUT std_logic_vector (3 DOWNTO 0);
     cout: OUT std_logic);
END adder;

ARCHITECTURE struct OFadder IS
SIGNAL c : std_logic_vector (4 DOWNTO 0);
BEGIN
     interm<=a XOR b;
     c<=((a AND b) OR (interm AND c(3 DOWNTO 0))) & '0';
     sum<= interm XOR c(3 DOWNTO 0);
     cout<=c(4);
END struct;