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  1.  wire clk_pll_raw,clk_pll,Q1A,Q2A,Q1B,Q2B;
  2.           wire CLK_A,CLK_A_raw,CLK_B,CLK_B_raw;
  3.          
  4.           IBUFDS IBUFDS_CLKA(.O(CLK_A_raw),.I(CLK_A_P),.IB(CLK_A_N));
  5.           BUFG CLKA(.O(CLK_A),.I(CLK_A_raw));
  6.  
  7.           IBUFDS IBUFDS_CLKB(.O(CLK_B_raw),.I(CLK_B_P),.IB(CLK_B_N));
  8.           BUFG CLKB(.O(CLK_B),.I(CLK_B_raw));
  9.  
  10.          
  11.           IBUFDS IBUFDS_clkpll(.O(clk_pll_raw),.I(CLK_P),.IB(CLK_N));
  12.           BUFG BUFG_clkpll(.I(clk_pll_raw),.O(clk_pll));
  13.           IBUFDS IBUFDS_Q1A (.O(Q1A), .I(Q1A_P), .IB(Q1A_N));
  14.           IBUFDS IBUFDS_Q2A (.O(Q2A), .I(Q2A_P), .IB(Q2A_N));
  15.           IBUFDS IBUFDS_Q1B (.O(Q1B), .I(Q1B_P), .IB(Q1B_N));
  16.           IBUFDS IBUFDS_Q2B (.O(Q2B), .I(Q2B_P), .IB(Q2B_N));
  17.  
  18.  
  19.           //
  20.           reg reset_MEM = 1'b1;
  21.           integer rst_counter_mem =0;
  22.           always @ ( posedge clk )
  23.           begin
  24.              if (rst_counter_mem < 100000)
  25.              begin
  26.                  reset_MEM <=  1'b1;
  27.                  rst_counter_mem = rst_counter_mem +1;
  28.              end
  29.              else  reset_MEM <= 1'b0;
  30.           end
  31.  
  32.  
  33.  
  34.  
  35.      
  36.  
  37.  
  38.           //Definitions of MEM1 inputs
  39.           wire clk_mem1,clk_obs1;
  40.         //   assign clk_obs1 = Q1A;  //Here
  41.         //   assign clk_mem1 = clk_pll&(~reset_MEM);
  42.           assign clk_obs1 = clk_5000;  //Here
  43.           assign clk_mem1 = CLK_A&(~reset_MEM);
  44.  
  45.  
  46.  
  47.           reg [31:0] counter1=32'b0;
  48.           always @(posedge clk_mem1)   //Here
  49.           begin
  50.           counter1 <= counter1+1'b1;
  51.           end
  52.  
  53.  
  54.           reg [31:0] write_loc1=32'b0;
  55.           reg pre_state1 = 1'b0;
  56.           reg flipped1= 1'b0;
  57.  
  58.           always @(negedge clk_mem1)   //Here
  59.           begin
  60.  
  61.           // initialising the clock with the original state
  62.           if(flipped1 == 0)
  63.           begin
  64.            pre_state1 <= clk_obs1;
  65.            flipped1<=1'b1;
  66.           end //if
  67.  
  68.           else if (pre_state1 == ~clk_obs1)//Checking if the state was changed
  69.           begin
  70.            pre_state1<=clk_obs1;
  71.  
  72.           //Writing to MEM
  73.           if(write_loc1 < MEM_DEPTH)
  74.           begin
  75.               MEM1[write_loc1] <= 32'd12345678;//counter1;
  76.               write_loc1<= write_loc1+1'b1;
  77.           end //if
  78.  
  79.           end //elseif
  80.           end //always
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