mathiaspl20

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May 3rd, 2020
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  1. -----------------------------------------------------------
  2. -- Titel            : Homework 2 - Sommersemester 19
  3. --                  : Thomas Mueller-W.
  4. -----------------------------------------------------------
  5. -- Aufgabe          : Aufgabe 2 - ALU entity/architecture
  6. -- StudentIn        : d
  7. -- Matrikelnummer   : d
  8. -----------------------------------------------------------
  9. library work;
  10. use work.all;
  11.  
  12. entity ALU is
  13.    port (
  14.      iSrcA      : in  bit_vector;
  15.      iSrcB      : in  bit_vector;
  16.      iALUControl: in  bit_vector(1  downto 0);
  17.      oALUResult : out bit_vector;
  18.      oZero      : out bit);
  19. end ALU;
  20.  
  21. architecture Behave of ALU is
  22.  
  23.     -- ======= Editierbereich Beginn ========================
  24.    
  25.     -- iALUControl: "00": Add, "01": Sub, "10": And, "11": Or
  26.  
  27.     procedure addBV  (
  28.         inBVa: in bit_vector;
  29.         inBVb: in bit_vector;
  30.         signal outBV: out bit_vector;
  31.         signal oZ: out bit
  32.     ) is
  33.         variable var : bit_vector(outBv'left to outBV'right) := (others => '0');
  34.         variable carry :bit := '0';
  35.     begin
  36.         oZ <= '1';
  37.         for i in var'range loop
  38.                 var(i) :=  inBVa(i) xor inBVb(i) xor carry;
  39.                 carry :=  (inBVa(i) and inBVb(i) ) or (carry and (inBVa(i) xor inBVb(i)));
  40.             if var(i) = '1' then
  41.                 oZ <= '0';
  42.             end if;
  43.         end loop;
  44.         outBv <= var;
  45.     end procedure;
  46.  
  47.     procedure subBV  (
  48.         inBVa: in bit_vector;
  49.         inBVb: in bit_vector;
  50.         signal outBV: out bit_vector;
  51.         signal oZ: out bit
  52.     ) is
  53.         variable var : bit_vector(outBv'left to outBV'right) := (others => '0');
  54.         variable carry :bit := '0';
  55.     begin
  56.         oZ <= '1';
  57.         for i in var'range loop
  58.                 var(i) :=  inBVa(i) xor inBVb(i) xor carry;
  59.                 carry :=  ((not inBVa(i)) and (inBVb(i) or carry)) or (carry and inBVb(i));
  60.  
  61.             if var(i) = '1' then
  62.                 oZ <= '0';
  63.             end if;
  64.         end loop;
  65.         outBv <= var;
  66.     end procedure;
  67.  
  68.     signal A : bit_vector(iSrcB'range) := iSrcA;
  69.     signal B : bit_vector(iSrcB'range) := iSrcB;
  70.     signal O : bit_vector(iSrcB'left to iSrcB'right+1);
  71.     signal C : bit;
  72.  
  73.     begin
  74.         process (iALUControl, iSrcA, iSrcB)
  75.             begin
  76.                 case iALUControl is
  77.                     when "00" =>--add
  78.                         addBV(A, B, O, C);
  79.                         oALUResult <= inertial  O after 15 ns;
  80.                         oZero <= inertial C after 10 ns;
  81.                     when "01" =>--sub
  82.                         subBV(A, B, O, C);
  83.                         oALUResult <= O;
  84.                         oZero <= inertial C after 10 ns;
  85.                     when "10" =>--and
  86.                         oALUResult <= inertial iSrcA and iSrcB after 15 ns;
  87.                         oZero <= inertial '1' after 10 ns;
  88.                     when "11" =>--or
  89.                         oALUResult <= inertial iSrcA or iSrcB after 15 ns;
  90.                         oZero <= inertial '1' after 10 ns;
  91.                  end case;
  92.             end process;
  93.        
  94.  
  95.     -- ======= Editierbereich Ende ===========================
  96.  
  97. end architecture Behave;
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