csm16_tb

-- Descrição do contador síncrono módulo 16
library ieee;
use ieee.std_logic_1164.all;

entity csm16_tb is
end csm16_tb;

architecture teste of csm16_tb is
    component csm16 is
        port(
            clock: in std_logic;
            clear: in std_logic;
            enable: in std_logic;
            q: out std_logic_vector(3 downto 0)
        );
    end component;
    signal clk: std_logic := '0'; --clock
    signal rst: std_logic := '0'; --clear
    signal hab: std_logic := '1'; --enable
    signal saida: std_logic_vector(3 downto 0); --q
    begin
        dut: csm16 port map(clk,rst,hab,saida);
        process (clk)
            begin
                clk <= not(clk) after 10 ns;
            end process;
        rst <= '1' after 50 ns;
        hab <= '0' after 130 ns, '1' after 170 ns;
end teste;