module controlCommand (
    input clk,  // clock
    input rst,  // reset
    input [8:0] cmd,
    output oe,
    output cl,
    output la,
    output busy
  );

  assign oe = regOe;
  assign cl = regCl;
  assign la = regLa;
  assign busy = regBusy;

  reg regOe;
  reg regCl;
  reg regLa;
  reg regBusy;

  reg [10:0] cnt;


  always @(negedge clk) begin
      cnt = cnt + 1;
      regCl <= 1'b0;
  end

  /* Sequential Logic */
  always @(posedge clk) begin
    if (rst) begin
      // Add flip-flop reset values here
    end else begin
      if(cmd > 0) begin
        regBusy <= 1'b1;
        if(cnt == 0) begin
          regLa <= 1'b1;
        end else if(cnt < (cmd + 1)) begin
          regCl <= 1'b1;
        end else if(cnt > cmd) begin
          regLa <= 1'b0;
          regBusy <= 1'b0;
        end
      end
    end
  end

endmodule