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JuanPZ

UBoot Log

JuanPZ
Nov 4th, 2021
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  1. =~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2021.11.04 11:10:51 =~=~=~=~=~=~=~=~=~=~=~=
  2.  
  3.  
  4. ===================================================================
  5.  
  6. MT7621 stage1 code Mar 12 2015 14:42:52 (ASIC)
  7.  
  8. CPU=50000000 HZ BUS=16666666 HZ
  9.  
  10. ==================================================================
  11.  
  12. Change MPLL source from XTAL to CR...
  13.  
  14. do MEMPLL setting..
  15.  
  16. MEMPLL Config : 0x11100000
  17.  
  18. 3PLL mode + External loopback
  19.  
  20. === XTAL-40Mhz === DDR-1200Mhz ===
  21.  
  22. PLL4 FB_DL: 0x1, 1/0 = 672/352 05000000
  23.  
  24. PLL3 FB_DL: 0xf, 1/0 = 624/400 3D000000
  25.  
  26. PLL2 FB_DL: 0x17, 1/0 = 568/456 5D000000
  27.  
  28. do DDR setting..[00320381]
  29.  
  30. Apply DDR3 Setting...(use customer AC)
  31.  
  32. 0 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120
  33.  
  34. --------------------------------------------------------------------------------
  35.  
  36. 0000:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  37.  
  38. 0001:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  39.  
  40. 0002:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  41.  
  42. 0003:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  43.  
  44. 0004:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  45.  
  46. 0005:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  47.  
  48. 0006:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  49.  
  50. 0007:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  51.  
  52. 0008:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  53.  
  54. 0009:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  55.  
  56. 000A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  57.  
  58. 000B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  59.  
  60. 000C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  61.  
  62. 000D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
  63.  
  64. 000E:| 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
  65.  
  66. 000F:| 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0
  67.  
  68. 0010:| 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
  69.  
  70. 0011:| 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  71.  
  72. 0012:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  73.  
  74. 0013:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  75.  
  76. 0014:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  77.  
  78. 0015:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  79.  
  80. 0016:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  81.  
  82. 0017:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  83.  
  84. 0018:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  85.  
  86. 0019:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  87.  
  88. 001A:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  89.  
  90. 001B:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  91.  
  92. 001C:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  93.  
  94. 001D:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  95.  
  96. 001E:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  97.  
  98. 001F:| 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
  99.  
  100. DRAMC_DQSCTL1[0e0]=13000000
  101.  
  102. DRAMC_DQSGCTL[124]=80000033
  103.  
  104. rank 0 coarse = 15
  105.  
  106. rank 0 fine = 56
  107.  
  108. B:| 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0
  109.  
  110. opt_dle value:9
  111.  
  112. DRAMC_DDR2CTL[07c]=C287221D
  113.  
  114. DRAMC_PADCTL4[0e4]=000022B3
  115.  
  116. DRAMC_DQIDLY1[210]=0D0D0A0E
  117.  
  118. DRAMC_DQIDLY2[214]=0B0F0C0D
  119.  
  120. DRAMC_DQIDLY3[218]=0B0A070B
  121.  
  122. DRAMC_DQIDLY4[21c]=09090C0A
  123.  
  124. DRAMC_R0DELDLY[018]=00002121
  125.  
  126. ==================================================================
  127.  
  128. RX DQS perbit delay software calibration
  129.  
  130. ==================================================================
  131.  
  132. 1.0-15 bit dq delay value
  133.  
  134. ==================================================================
  135.  
  136. bit| 0 1 2 3 4 5 6 7 8 9
  137.  
  138. --------------------------------------
  139.  
  140. 0 | 13 10 11 13 12 10 15 10 9 7
  141.  
  142. 10 | 10 10 10 11 9 7
  143.  
  144. --------------------------------------
  145.  
  146.  
  147.  
  148. ==================================================================
  149.  
  150. 2.dqs window
  151.  
  152. x=pass dqs delay value (min~max)center
  153.  
  154. y=0-7bit DQ of every group
  155.  
  156. input delay:DQS0 =33 DQS1 = 33
  157.  
  158. ==================================================================
  159.  
  160. bit DQS0 bit DQS1
  161.  
  162. 0 (1~64)32 8 (1~62)31
  163.  
  164. 1 (1~65)33 9 (1~65)33
  165.  
  166. 2 (0~62)31 10 (1~65)33
  167.  
  168. 3 (1~66)33 11 (1~64)32
  169.  
  170. 4 (1~63)32 12 (1~66)33
  171.  
  172. 5 (1~62)31 13 (1~64)32
  173.  
  174. 6 (1~64)32 14 (1~65)33
  175.  
  176. 7 (1~63)32 15 (1~62)31
  177.  
  178. ==================================================================
  179.  
  180. 3.dq delay value last
  181.  
  182. ==================================================================
  183.  
  184. bit| 0 1 2 3 4 5 6 7 8 9
  185.  
  186. --------------------------------------
  187.  
  188. 0 | 14 10 13 13 13 12 15 11 11 7
  189.  
  190. 10 | 10 11 10 12 9 9
  191.  
  192. ==================================================================
  193.  
  194. ==================================================================
  195.  
  196. TX perbyte calibration
  197.  
  198. ==================================================================
  199.  
  200. DQS loop = 15, cmp_err_1 = ffff0000
  201.  
  202. dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1
  203.  
  204. dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2
  205.  
  206. DQ loop=15, cmp_err_1 = ffff0000
  207.  
  208. dqs_perbyte_dly.last_dqdly_pass[0]=15, finish count=1
  209.  
  210. dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=2
  211.  
  212. byte:0, (DQS,DQ)=(8,8)
  213.  
  214. byte:1, (DQS,DQ)=(8,8)
  215.  
  216. DRAMC_DQODLY1[200]=88888888
  217.  
  218. DRAMC_DQODLY2[204]=88888888
  219.  
  220. 20,data:88
  221.  
  222. [EMI] DRAMC calibration passed
  223.  
  224.  
  225.  
  226.  
  227. ===================================================================
  228.  
  229. MT7621 stage1 code done
  230.  
  231. CPU=50000000 HZ BUS=16666666 HZ
  232.  
  233. ===================================================================
  234.  
  235.  
  236.  
  237. U-Boot 1.1.3 (Dec 18 2019 - 16:44:40)
  238.  
  239.  
  240. Board: Ralink APSoC DRAM: 128 MB
  241.  
  242. relocate_code Pointer at: 87f90000
  243.  
  244.  
  245. Config XHCI 40M PLL
  246.  
  247. Allocate 16 byte aligned buffer: 87fc8130
  248.  
  249. Enable NFI Clock
  250.  
  251. # MTK NAND # : Use HW ECC
  252.  
  253. NAND ID [EF F1 00 95 00]
  254.  
  255. Device found in MTK table, ID: eff1, EXT_ID: 9500
  256.  
  257. Support this Device in MTK table! eff1
  258.  
  259. select_chip
  260.  
  261. [NAND]select ecc bit:4, sparesize :64 spare_per_sector=16
  262.  
  263. Signature matched and data read!
  264.  
  265. load_fact_bbt success 1023
  266.  
  267. load fact bbt success
  268.  
  269. [mtk_nand] probe successfully!
  270.  
  271. mtd->writesize=2048 mtd->oobsize=64, mtd->erasesize=131072 devinfo.iowidth=8
  272.  
  273. ..============================================
  274.  
  275. Ralink UBoot Version: 5.0.0.0
  276.  
  277. --------------------------------------------
  278.  
  279. ASIC MT7621A DualCore (MAC to MT7530 Mode)
  280.  
  281. DRAM_CONF_FROM: Auto-Detection
  282.  
  283. DRAM_TYPE: DDR3
  284.  
  285. DRAM bus: 16 bit
  286.  
  287. Xtal Mode=3 OCP Ratio=1/3
  288.  
  289. Flash component: 4 MBytes NOR Flash
  290.  
  291. Date:Dec 18 2019 Time:16:44:40
  292.  
  293. ============================================
  294.  
  295. icache: sets:256, ways:4, linesz:32 ,total:32768
  296.  
  297. dcache: sets:256, ways:4, linesz:32 ,total:32768
  298.  
  299.  
  300. ##### The CPU freq = 880 MHZ ####
  301.  
  302. estimate memory size =128 Mbytes
  303.  
  304. #Reset_MT7530
  305.  
  306. set LAN/WAN LLLLW
  307.  
  308. ########BUTTON_RESET: 15
  309.  
  310.  
  311. =================================================
  312.  
  313. Check image validation:hdr1_addr[bc180000]hdr2_addr[c0980000]
  314.  
  315. Image1 Header Magic Number --> OK
  316.  
  317. Image2 Header Magic Number --> OK
  318.  
  319. Image1 Header Checksum --> OK
  320.  
  321. Image2 Header Checksum --> OK
  322.  
  323. Image1 Data Checksum --> .................................................OK
  324.  
  325. ..Erasing NAND Flash...
  326.  
  327. ranand_erase: start:80000, len:20000
  328.  
  329. .Writing to NAND Flash...
  330.  
  331. done
  332.  
  333. Image2 Data Checksum --> .................................................OK
  334.  
  335. Image1 Stable Flag --> Stable
  336.  
  337. Image1 Try Counter --> 0
  338.  
  339.  
  340. Image1: OK Image2: OK
  341.  
  342.  
  343. =================================================
  344.  
  345.  
  346. Please choose the operation:
  347.  
  348. 1: Load system code to SDRAM via TFTP.
  349.  
  350. 2: Load system code then write to Flash via TFTP.
  351.  
  352. 3: Boot system code via Flash (default).
  353.  
  354. 4: Entr boot command line interface.
  355.  
  356. 6: System Enter UBoot to Update Img.
  357.  
  358. 7: Load Boot Loader code then write to Flash via Serial.
  359.  
  360. 9: Load Boot Loader code then write to Flash via TFTP.
  361.  
  362. default: 3
  363.  
  364.  0
  365.  
  366.  
  367.  
  368. 3: System Boot system code via Flash.
  369.  
  370. ## Booting image at bc180000 ...
  371.  
  372. Image Name: DIR-2150
  373.  
  374. Image Type: MIPS Linux Kernel Image (lzma compressed)
  375.  
  376. Data Size: 3175627 Bytes = 3 MB
  377.  
  378. Load Address: 81001000
  379.  
  380. Entry Point: 81001000
  381.  
  382. ................................................. Verifying Checksum ... OK
  383.  
  384. Uncompressing Kernel Image ... OK
  385.  
  386. No initrd
  387.  
  388. ## Transferring control to Linux (at address 81001000) ...
  389.  
  390. ## Giving linux memsize in MB, 128
  391.  
  392.  
  393. Starting kernel ...
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