library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

--
-- Vanjsko sucelje prilagodjeno nazivima tipki plocice ULX2S.
-- Za rad na plocici ULX2S, umjesto btn_center koristite btn_f1.
--

entity datapath is
    generic (
	C_data_width: integer := 4
    );
    port (
	btn_left, btn_right, btn_center, btn_up, btn_down: in std_logic;
	sw: in std_logic_vector(3 downto 0);
	clk_25m: in std_logic;
	led: out std_logic_vector(7 downto 0)
    );
end datapath;
--AddrA=Strahomir,AddrB=Ratomir,AddrW=Strahomir,ALUOp=Stanislava,Clk=Vlado,A=x,B=y,Z=z,W=j,Bmux=Dunav
architecture x of datapath is
    signal Strahomir, Ratomir: std_logic_vector(1 downto 0);
    signal Stanislava: std_logic_vector(2 downto 0);
    signal Vlado: std_logic;
    signal x, y, z, j, Dunav: std_logic_vector((C_data_width - 1) downto 0);

begin

    I_regfile: entity reg_file
    generic map (
	C_data_width => C_data_width
    )
    port map (
	AddrA => Strahomir, AddrB => Ratomir, AddrW => Strahomir,
	WE => '1', Clk => Vlado,
	A => x, B => y, W => j
    );

    I_upravljac: entity upravljac
    port map (
	Clk_key => btn_up,
	AddrA_key => btn_left,
	AddrB_key => btn_right,
	ALUOp_key => btn_down,
	clk_25m => clk_25m,
	AddrA => Strahomir,
	AddrB => Ratomir,
	ALUOp => Stanislava,
	Clk => Vlado
    );

    led(7 downto 4) <=Strahomir & Ratomir when btn_center = '0' else x;
    led(3 downto 0) <= Vlado & Stanislava when btn_center = '0' else y;

    ALU: entity alu
	port map(
	   ALU_A => x,
	   ALU_B => y,
	   ALU_Z => z,
	   ALUOp => Stanislava
	);

    with Ratomir select
    Dunav <=
           sw  when   "00",
	   y   when others;
end;