Lab8

library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pwm is
    port( writedata: in std_logic_vector(31 downto 0);
        clk_clk, reset_reset_n:   in std_logic;
        wr, cs : in std_logic;
        display: out std_logic_vector(6 downto 0);
        led: out std_logic_vector(1 downto 0)
    );
end pwm;

architecture rtl of pwm is
    signal reg: std_logic_vector(4 downto 0);
begin

    process(clk_clk)
    begin
       if (clk_clk'event and clk_clk = '1') then
            if (wr = '1' and cs = '1') then
                reg <= writedata(4 downto 0);
            end if;
        end if;
    end process;

    process(clk_clk)
    begin
        if (clk_clk'event and clk_clk = '1') then
            CASE reg IS
                WHEN "00000" => display <= "1000000";   --0
                WHEN "00001" => display <= "1111001";   --1
                WHEN "00010" => display <= "0100100";   --2
                WHEN "00011" => display <= "0110000";   --3
                WHEN "00100" => display <= "0011001";   --4
                WHEN "00101" => display <= "0010010";   --5
                WHEN "00110" => display <= "0000010";   --6
                WHEN "00111" => display <= "1111000";   --7
                WHEN "01000" => display <= "0000000";   --8
                WHEN "01001" => display <= "0010000";   --9
                WHEN OTHERS => display <=  "0000110";   --E
            END CASE;

            if (reg = "00000") then
                LED <= "00";
            elsif (reg = "00001" or reg = "00010" or reg = "00011" or reg = "00100" or reg = "00101" or reg = "00110"  or reg = "00111"  or reg = "01000"  or reg = "01001") then
                LED <= "01"; -- led swieci
            elsif (reg = "10001" or reg = "10010" or reg = "10011" or reg = "10100" or reg = "10101" or reg = "10110"  or reg = "10111"  or reg = "11000"  or reg = "11001"  or reg = "11010")
                then LED <= "11"; --led i error swieci
            else
                LED <= "10"; -- error swieci
            end if;
        end if;
    end process;

end rtl;