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- import migen.fhdl.verilog
- import migen.bus.wishbone
- import milkymist.lm32
- cpu = milkymist.lm32.Inst()
- sharedbus = migen.bus.wishbone.Master()
- arbiter = migen.bus.wishbone.Arbiter([cpu.ibus, cpu.dbus], sharedbus)
- frag = cpu.GetFragment() + arbiter.GetFragment()
- print(migen.fhdl.verilog.Convert(frag))
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