LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY LogicalStep_Lab4_top IS PORT
    (
   clkin_50     : in    std_logic;
    rst_n           : in    std_logic;
    pb              : in    std_logic_vector(3 downto 0);
    sw              : in  std_logic_vector(7 downto 0); -- The switch inputs
   leds         : out std_logic_vector(7 downto 0); -- for displaying the switch content
   seg7_data    : out std_logic_vector(6 downto 0); -- 7-bit outputs to a 7-segment
    seg7_char1  : out   std_logic;                          -- seg7 digi selectors
    seg7_char2  : out   std_logic                           -- seg7 digi selectors
    );
END LogicalStep_Lab4_top;



ARCHITECTURE SimpleCircuit OF LogicalStep_Lab4_top IS

----------------------------------------------------------------------------------------------------
    CONSTANT    SIM                         :  boolean := TRUE;     -- set to TRUE for simulation runs otherwise keep at 0.
   CONSTANT CLK_DIV_SIZE                :   INTEGER := 26;    -- size of vectors for the counters

   SIGNAL   Main_CLK                        :  STD_LOGIC;           -- main clock to drive sequencing of State Machine

    SIGNAL  bin_counter                 :  UNSIGNED(CLK_DIV_SIZE-1 downto 0); -- := to_unsigned(0,CLK_DIV_SIZE); -- reset binary counter to zero

----------------------------------------------------------------------------------------------------

component U_D_Bin_Counter8bit port(
    CLK             : in std_logic := '0';
        RESET_n         : in std_logic := '0';
        CLK_EN          : in std_logic := '0';
        UP1_DOWN0       : in std_logic := '0';
        COUNTER_BITS    : out std_logic_vector(7 downto 0)
);
end component;

component Bidir_shift_reg port(
    CLK             : in std_logic := '0';
    RESET_n         : in std_logic := '0';
    CLK_EN          : in std_logic := '0';
    LEFT0_RIGHT1: in std_logic := '0';
    REG_BITS    : out std_logic_vector(7 downto 0)
);
end component;

component SevenSegment port (
   hex      :  in  std_logic_vector(3 downto 0);   -- The 4 bit data to be displayed
   sevenseg     :  out std_logic_vector(6 downto 0)    -- 7-bit outputs to a 7-segment
);
end component;

component segment7_mux port (
   clk          : in  std_logic := '0';
    DIN2            : in  std_logic_vector(6 downto 0);
    DIN1            : in  std_logic_vector(6 downto 0);
    DOUT            : out   std_logic_vector(6 downto 0);
    DIG2            : out   std_logic;
    DIG1            : out   std_logic
);
end component;

component Compx4 port(
    CURRENT             : in std_logic_vector(3 downto 0); --MUST RENAME
    DESIRED             : in std_logic_vector(7 downto 4);
    FURNACE_ON          : out std_logic;
    AT_TEMP             : out std_logic;
    AC_ON                   : out std_logic
);
end component;

component mux port(
    CURRENT_X    : in std_logic_vector (3 downto 0);
   TARGET_X   : in std_logic_vector (3 downto 0);
   PB         : in std_logic;
   OUT1       : out std_logic_vector (3 downto 0)
);
end component;

    -- input signals
    signal target_x     : std_logic_vector(7 downto 4);
    signal target_y     : std_logic_vector(3 downto 0);
    signal x_drive_en       : std_logic;
    signal y_drive_en       : std_logic;
    signal ext_toggle       : std_logic;
    signal grap_toggle  : std_logic;

    --output signals
    signal digit_1          : std_logic;
    signal digit_2          : std_logic;
    signal ext_pos          : std_logic_vector(7 downto 4);
    signal grappler_on  : std_logic;
    signal TBD              : std_logic_vector(2 downto 1); --manual says "for your use", unsure as to what that means right now
    signal error            : std_logic;
    signal x_display        : std_logic; -- these are the two output signals from the mux
    signal y_display        : std_logic; -- to be displayed on seven seg display


BEGIN

    -- input signals
    target_x        <= sw(7 downto 4);
    target_y        <= sw(3 downto 0);
    x_drive_en  <= pb(3);
    y_drive_en  <= pb(2);
    ext_toggle  <= pb(1);
    grap_toggle <= pb(0);

    --output signals
    seg7_char1          <= digit_1;
    seg7_char2          <= digit_2;
    leds(7 downto 4)    <= ext_pos;
    leds(3)                 <= grappler_on;
    leds(2 downto 1)    <= TBD;
    leds(0)                 <= error;

    --X_VAL_MUX: mux( );
--  --Y_VAL_MUX: mux( );
--  CURRENT             : std_logic_vector(3 downto 0); --MUST RENAME
--  DESIRED             : std_logic_vector(7 downto 4);
--  FURNACE_ON          : std_logic;
--  AT_TEMP             : std_logic;
--  AC_ON                   : std_logic;



    -- FIGURE OUT CONNECTIONS   SHIFT_REGISTER:



-- CLOCKING GENERATOR WHICH DIVIDES THE INPUT CLOCK DOWN TO A LOWER FREQUENCY

BinCLK: PROCESS(clkin_50, rst_n) is
   BEGIN
        IF (rising_edge(clkin_50)) THEN -- binary counter increments on rising clock edge
         bin_counter <= bin_counter + 1;
      END IF;
   END PROCESS;

Clock_Source:
                Main_Clk <=
                --clkin_50 when sim = TRUE else             -- for simulations only
                std_logic(bin_counter(23));                             -- for real FPGA operation

---------------------------------------------------------------------------------------------------

--  COUNTER:    U_D_Bin_Counter8bit port map();
--  COMPX4 :    Compx4 port map();
--  --MEALY_SM:     Mealy_SM port map(clkin_50, rst_n, x_drive_en,  );
--  SEVEN_SEG:  SevenSegment port map();

END SimpleCircuit;