//verilog code

module moore_fsm (clock, x, z);

input clock, x;

output reg z;

reg [2:0] present_state, next_state;

always @ (posedge clock)

   present_state <= next_state;


always @ (present_state or x)

begin

   case(present_state)

       3'b000: begin z <= 1'b0; if (~x) next_state <= 3'b001; else next_state <= 3'b000; end
       3'b001: begin z <= 1'b0; if (x) next_state <= 3'b010; else next_state <= 3'b001; end
       3'b010: begin z <= 1'b0; if (~x) next_state <= 3'b011; else next_state <= 3'b000; end
       3'b011: begin z <= 1'b1; if (x) next_state <= 3'b100; else next_state <= 3'b011; end
       3'b100: begin z <= 1'b1; if (~x) next_state <= 3'b000; else next_state <= 3'b101; end
       3'b101: begin z <= 1'b1; if (~x) next_state <= 3'b011; else next_state <= 3'b101; end
       default: next_state <= 3'b000;
   endcase

end

endmodule

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

//testbench

module tb_moore_fsm();

reg clock, x;

wire z;

moore_fsm uut(clock, x, z);

initial
begin
   x = 1;
   #25;
   x = 1;
   #25;
   x = 0;
   #25;
   x = 0;
   #25;
   x = 1;
   #25;
   x = 0;
   #25;
   x = 1;
   #25;
   x = 0;
   #25;
   x = 1;
   #25;
   x = 0;
   #25;
   x = 0;
   #25;

end

always
begin
   clock = 1;
   #10;
   clock = 0;
   #10;
end

endmodule