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- static void SystemClock_Config(void)
- {
- /* Enable Power Control clock */
- RCC->APB1ENR |= 0x10000000; // Enable PWREN bit (page - 183 of RM)
- /* The voltage scaling allows optimizing the power consumption when the device is
- clocked below the maximum system frequency, to update the voltage scaling value
- regarding system frequency refer to product datasheet. */
- PWR->CR |= 0x00004000; //VOS bit = 01 (page - 145 or RM)
- // Page - 216 of RM
- RCC->CR |= 0x00010000; // HSE ON
- while((RCC->CR & 0x00020000) == 0); // Wait till HSE is ready
- /* Enable HSI Oscillator and activate PLL with HSI as source */
- // Page - 226 of RM
- RCC->PLLCFGR = 0;
- RCC->PLLCFGR |= 0x00400000; // PLL source is HSE
- RCC->PLLCFGR |= 0x00000008; // M = 8
- RCC->PLLCFGR |= 0x00000000 + ((uint32_t)336 << 6); // N = 336
- RCC->PLLCFGR |= 0x00000000 + (((uint32_t)2 >> 1) - 1); // P = 2
- RCC->PLLCFGR |= 0x00000000 + ((uint32_t)7 << 24); // Q = 7
- RCC->CR |= 0x01000000; // PLL ON
- while((RCC->CR & 0x02000000) == 0); // Wait till PLL is ready
- /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
- clocks dividers */
- /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
- RCC->CFGR |= 0x00000000; // HPRE = 0 = Div by 1 (no division), AHB = 168MHz
- RCC->CFGR |= 0x00000000 + ((uint32_t)5 << 10); // PPRE1 = 5, APB1 = div by 4 = 42MHz
- RCC->CFGR |= 0x00000000 + ((uint32_t)4 << 13); // PPRE2 = 4, APB2 = div by 2 = 84MHz
- volatile uint32_t temp = RCC->CFGR;
- temp = temp | 0x00000002;
- RCC->CFGR = temp;
- //while((RCC->CFGR & 0x00000008) == 0); // Make sure SWS = 0b10 = PLL is really selected
- FLASH->ACR|= 0x000000055; // FLASH_LATENCY_5
- /* STM32F405x/407x/415x/417x Revision Z devices: prefetch is supported */
- volatile uint32_t idNumber = DBGMCU->IDCODE;
- idNumber = idNumber >> 16;
- /* Enable the Flash prefetch */
- if(idNumber == 0x1001)
- {
- FLASH->ACR |= 0x00000100;
- }
- }
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