MrRockchip

mainboard.c

Oct 14th, 2020
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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2.  
  3. #include "ec.h"
  4.  
  5. #include <acpi/acpi.h>
  6. #include <console/console.h>
  7. #include <cpu/x86/smm.h>
  8. #include <device/device.h>
  9.  
  10. #include <southbridge/amd/agesa/hudson/pci_devs.h>
  11. #include <southbridge/amd/agesa/hudson/amd_pci_int_defs.h>
  12. #include <southbridge/amd/common/amd_pci_util.h>
  13. #include <northbridge/amd/agesa/family15tn/pci_devs.h>
  14. #include <southbridge/amd/agesa/hudson/smi.h>
  15.  
  16. static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
  17.     /* INTA# - INTH# */
  18.     [0x00] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F,
  19.     /* Misc-nil,0,1,2, INT from Serial irq */
  20.     [0x08] = 0x5A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
  21.     /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
  22.     [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,
  23.     /* IMC INT0 - 5 */
  24.     [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
  25.     /* USB Devs 18/19/22 INTA-B */
  26.     [0x30] = 0x05,0x04,0x05,0x04,0x05,0x04,0x1F,0x1F,
  27.     /* RSVD, SATA */
  28.     [0x40] = 0x1F, 0x07
  29. };
  30.  
  31. static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = {
  32.     /* INTA# - INTH# */
  33.     [0x00] = 0x10,0x11,0x12,0x13,0x1F,0x1F,0x1F,0x1F,
  34.     /* Misc-nil,0,1,2, INT from Serial irq */
  35.     [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
  36.     /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */
  37.     [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x1F,
  38.     /* IMC INT0 - 5 */
  39.     [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
  40.     /* USB Devs 18/19/22 INTA-B */
  41.     [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x1F,0x1F,
  42.     /* RSVD, SATA */
  43.     [0x40] = 0x1F, 0x13
  44. };
  45.  
  46. /*
  47.  * This table defines the index into the picr/intr_data
  48.  * tables for each device.  Any enabled device and slot
  49.  * that uses hardware interrupts should have an entry
  50.  * in this table to define its index into the FCH
  51.  * PCI_INTR register 0xC00/0xC01.  This index will define
  52.  * the interrupt that it should use.  Putting PIRQ_A into
  53.  * the PIN A index for a device will tell that device to
  54.  * use PIC IRQ 10 if it uses PIN A for its hardware INT.
  55.  */
  56. static const struct pirq_struct mainboard_pirq_data[] = {
  57.     /* {PCI_devfn,  {PIN A, PIN B, PIN C, PIN D}}, */
  58.     {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}},           /* VGA:     01.0 */
  59.     {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}},           /* Audio:   01.1 */
  60.     {NB_PCIE_PORT1_DEVFN,   {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}},  /* x4 PCIe: 02.1 */
  61.     {NB_PCIE_PORT5_DEVFN,   {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}},  /* Edge:    02.5 */
  62.     {XHCI_DEVFN,    {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}},       /* XHCI:    10.0 */
  63.     {SATA_DEVFN,    {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},    /* SATA:    11.0 */
  64.     {OHCI1_DEVFN,   {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}},   /* OHCI1:   12.0 */
  65.     {EHCI1_DEVFN,   {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}},   /* EHCI1:   12.2 */
  66.     {OHCI2_DEVFN,   {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}},   /* OHCI2:   13.0 */
  67.     {EHCI2_DEVFN,   {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}},   /* EHCI2:   13.2 */
  68.     {OHCI3_DEVFN,   {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}},   /* OHCI3:   16.0 */
  69.     {EHCI3_DEVFN,   {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}},   /* EHCI3:   16.2 */
  70.     {HDA_DEVFN,     {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}},     /* HDA:     14.2 */
  71. };
  72.  
  73. const u8 *picr_data = mainboard_picr_data;
  74. const u8 *intr_data = mainboard_intr_data;
  75.  
  76. /* PIRQ Setup */
  77. static void pirq_setup(void)
  78. {
  79.     pirq_data_ptr = mainboard_pirq_data;
  80.     pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct);
  81.     intr_data_ptr = mainboard_intr_data;
  82.     picr_data_ptr = mainboard_picr_data;
  83. }
  84.  
  85. static void pavilion_cold_boot_init(void)
  86. {
  87.     /* Lid SMI is only used in non-ACPI mode; leave it off in S3 resume */
  88.     hudson_configure_gevent_smi(EC_LID_GEVENT, SMI_MODE_SMI, SMI_LVL_LOW);
  89.     /* EC is not powered off during S3 sleep */
  90.     lenovo_g505s_ec_init();
  91. }
  92.  
  93. /**********************************************
  94.  * enable the dedicated function in mainboard.
  95.  **********************************************/
  96. static void mainboard_enable(struct device *dev)
  97. {
  98.     printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
  99.  
  100.     /* Initialize the PIRQ data structures for consumption */
  101.     pirq_setup();
  102.  
  103.     hudson_configure_gevent_smi(EC_SMI_GEVENT, SMI_MODE_SMI, SMI_LVL_HIGH);
  104.     global_smi_enable();
  105.  
  106.     if (!acpi_is_wakeup_s3())
  107.         pavilion_cold_boot_init();
  108. }
  109.  
  110. struct chip_operations mainboard_ops = {
  111.     .enable_dev = mainboard_enable,
  112. };
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