--------------------------------
--- Full Adder Components
--- Dr. Amoo
--- 10/25/2017
--------------------------------
--------------------------------------
--- Full Adder -- First- bit- slice
--- Dr. Amoo
--- 10/25/201
--------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
ENTITY JOSEPH_First_BSlice IS
PORT (
Op_A :IN STD_LOGIC;
Op_B :IN STD_LOGIC;
SUM_Q :OUT STD_LOGIC;
Carry_Q :OUT STD_LOGIC
 );
END JOSEPH_First_BSlice;
ARCHITECTURE BEH_first_BS OF JOSEPH_First_BSlice IS
CONSTANT My_C: STD_LOGIC:='0';
BEGIN
SUM_Q <= OP_A XOR OP_B XOR My_C;
Carry_Q <= ((OP_A XOR OP_B) AND My_C) OR (OP_A AND OP_B);
END BEH_first_BS;

--------------------------------
--- Full Adder -- 1-bit slice
--- Dr. Amoo
--- 10/25/2017
--------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
ENTITY JOSEPH_FA_BSlice IS
PORT (
Op_A :IN STD_LOGIC;
Op_B :IN STD_LOGIC;
Op_C :IN STD_LOGIC;
SUM_Q :OUT STD_LOGIC;
Carry_Q :OUT STD_LOGIC
 );
END JOSEPH_FA_BSlice;

ARCHITECTURE BEH_BS OF JOSEPH_FA_BSlice IS
BEGIN
SUM_Q <= OP_A XOR OP_B XOR OP_C;
Carry_Q <= ((OP_A XOR OP_B) AND OP_C) OR (OP_A AND OP_B);
END BEH_BS;


--------------------------------------------------------------
-- Design: Generic inter-slice register for Full Adder
-- Name: Dr. Amoo
-- Date: 10/25/2017
--------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_Logic_1164.all;
ENTITY REG_FA IS
 GENERIC(P: integer:= 16;
 W: integer:= 4;
 E: integer:= 8);
PORT ( CLK :IN STD_LOGIC; --clk
Reset :IN STD_LOGIC; --reset
En :IN STD_LOGIC;
Op_A :IN STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_B :IN STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_Sum :IN STD_LOGIC_VECTOR(W-1 DOWNTO 0); -- sum
Op_Carry:IN STD_LOGIC; -- carry
Op_AQ :OUT STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_BQ :OUT STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_SQ :OUT STD_LOGIC_VECTOR(W-1 DOWNTO 0);
Op_C :OUT STD_LOGIC
 );
END REG_FA;

ARCHITECTURE RTL OF REG_FA IS
SIGNAL DA : STD_LOGIC_VECTOR(P-1 DOWNTO 0);
SIGNAL DB : STD_LOGIC_VECTOR(P-1 DOWNTO 0);
SIGNAL DS : STD_LOGIC_VECTOR(W-1 DOWNTO 0);
SIGNAL DC : STD_LOGIC;
BEGIN
P_REG_FA: PROCESS(Clk)
BEGIN

IF ((Clk'EVENT) AND (Clk= '1')) THEN
IF (Reset = '1') THEN
DA <= (OTHERS => '0');
DB <= (OTHERS => '0');
DS <= (OTHERS => '0');
DC <= '0';
ELSIF (En = '1') THEN
DA <= Op_A;
DB <= Op_B;
DS <= Op_Sum;
DC <= Op_Carry;
ELSE
DA <= DA;
DB <= DB;
DS <= DS;
DC <= DC;
END IF; -- reset
END IF; --clk = 1
END PROCESS P_REG_FA;
OP_AQ <= DA;
OP_BQ <= DB;
OP_SQ <= DS;
OP_C <= DC;
END RTL;


--------------------------------------------------------------
--------------------------------------------------------------
-- Design: Generic Last-slice register for Full Adder
-- Name: Dr. Amoo
-- Date: 10/25/2017
--------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_Logic_1164.all;
ENTITY REG_FA_lastslice IS
 GENERIC(P: integer:= 16;
 W: integer:= 4;
 E: integer:= 8);
PORT ( CLK :IN STD_LOGIC; --clk
Reset :IN STD_LOGIC; --reset
En :IN STD_LOGIC;
Op_A :IN STD_LOGIC; -- sign bit
Op_B :IN STD_LOGIC; -- sign bit
Op_Sum :IN STD_LOGIC_VECTOR(P-1 DOWNTO 0); -- sum
Op_Carry:IN STD_LOGIC; -- carry
Op_Q :OUT STD_LOGIC_VECTOR(P-1 DOWNTO 0);
Op_F :OUT STD_LOGIC_VECTOR(W-2 DOWNTO 0)
 );
END REG_FA_lastslice;

ARCHITECTURE RTL OF REG_FA_lastslice IS
--SIGNAL DA : STD_LOGIC;
--SIGNAL DB : STD_LOGIC;
SIGNAL DS : STD_LOGIC_VECTOR(P-1 DOWNTO 0);
SIGNAL DC : STD_LOGIC_VECTOR(W-2 DOWNTO 0);


BEGIN
P_REG_FA: PROCESS(Clk)
BEGIN

IF ((Clk'EVENT) AND (Clk= '1')) THEN
IF (Reset = '1') THEN
DS <= (OTHERS => '0');
DC <= (OTHERS => '0');
ELSIF (En = '1') THEN
DS <= Op_Sum;
DC <= Op_A & Op_B & Op_Carry;
ELSE
DS <= DS;
DC <= DC;
END IF; -- reset
END IF; --clk = 1
END PROCESS P_REG_FA;
OP_Q <= DS;
OP_F <= DC;
END RTL;