function famakin_regarray

% Plan of attack: Create an array of arrays where each array is a register
% A register is described by
% R = [DATA_IN | ENABLE | RESET | DATA_OUT]
%
% R(1) = OP_A, R(2) = EN, R(3) = RST, R(4) = OP_Q
% The array of registers is thus:
%
% [R0, R1 ... RN]
%
% Input file is of the form:
% ----------------------------------------
% OP_A | LD_REG | RESET | DR | SR1 | SR2
%
% - Make LD_REG fluctuate between 0 and 1
% - Make RESET 1 for a couple clock cycles
% - Declare a variable sEN which contains the ENABLE signals for
%   each register in the array

fin = fopen('FAMAKIN_REGARRAY_INPUT.txt', 'w');
fout = fopen('FAMAKIN_REGARRAY_OUTPUT.txt', 'w');

fprintf(fin, '%s\r\n', 'XXXXXXXXXXXXXXXX X X XXX XXX XXX');

%initialize regarray
regarray = cell(8, 1);

%create an array to hold last known values of the register
% just in case we want to latch
last_out = cell(8, 1);

%create your ENABLE vector signal
sEN = repmat('0', 1, 8);

for i = 1:8
    reg = {dec2bin(0, 16), '0', '1', dec2bin(i, 16)};
    regarray{i} = reg;
end

%test reset
for A = 0:3
    %always reset ENABLE vector to zeros
    %we only need one bit of the vector to be high at a time
    sEN = repmat('0', 1, 8);
    RESET = '1';
    dr = mod(A, 8);
    dr_bin = dec2bin(7-dr, 3);
    LD_REG = dec2bin(mod(A, 2), 1);
    sEN(dr + 1) = LD_REG;
    for i = 1:8
        regarray{i}{1} = dec2bin(A, 16);
        regarray{i}{2} = sEN(i);
        regarray{i}{3} = RESET;
        regarray{i}{4} = dec2bin(0, 16);
        last_out{i} = 0;
    end

    SR1 = mod(A+1, 8);
    SR2 = 7-mod(A, 8);

    SR1_bin = dec2bin(7-SR1, 3);
    SR2_bin = dec2bin(7-SR2, 3);

    file_input = [dec2bin(A, 16) ' ' LD_REG ' ' RESET ' ' dr_bin ' ' SR1_bin ' ' SR2_bin];
    fprintf(fin, '%s\r\n', file_input);
    fprintf(fout, '%s\r\n', [dec2bin(0, 16) ' ' dec2bin(0, 16)]);
end

for A = 4:7
    sEN = repmat('0', 1, 8);
    RESET = '0';

    %make dr go from 0 to 7
    dr = mod(A, 8);
    %remember MATLAB goes from 1-8 MSB-LSB
    %but VHDL goes from 7-0 MSB to LSB. So we
    %have to switch indexing systems
    dr_bin = dec2bin(7-dr, 3);
    %we're fluctuating the enable here
    LD_REG = dec2bin(mod(A+1, 2), 1);
    %assigning the only high enable to the destination register
    sEN(dr+1) = LD_REG;

    for i = 1:8
        regarray{i}{1} = dec2bin(A, 16);
        regarray{i}{2} = sEN(i);
        regarray{i}{3} = RESET;

        if regarray{i}{2} == '0'
            regarray{i}{4} = dec2bin(last_out{i}, 16);
        else
            regarray{i}{4} = dec2bin(A, 16);
            last_out{i} = bin2dec(regarray{i}{4});
        end
    end
    %this is to make sure that the source register
    %is not the same as the destination register
    SR1 = mod(A+1, 8);
    SR2 = 7-mod(A, 8);

    %also we're switching to VHDL's index system (7 downto 0)
    SR1_bin = dec2bin(7-SR1, 3);
    SR2_bin = dec2bin(7-SR2, 3);

    fprintf(fin, '%s\r\n', [dec2bin(A, 16) ' ' LD_REG ' ' RESET ' ' dr_bin ' ' SR1_bin ' ' SR2_bin]);
    fprintf(fout, '%s\r\n', [regarray{SR1+1}{4} ' ' regarray{SR2+1}{4}]);
end

for A = 8:100%(2^16)-1
   sEN = repmat('0', 1, 8);
   RESET = '0';
   dr = mod(A, 8);
   dr_bin = dec2bin(7-dr, 3);
   LD_REG = '1';
   sEN(dr+1) = LD_REG;

    for i = 1:8
        regarray{i}{1} = dec2bin(A, 16);
        regarray{i}{2} = sEN(i);
        regarray{i}{3} = RESET;

        if regarray{i}{2} == '0'
            regarray{i}{4} = dec2bin(last_out{i}, 16);
        else
            regarray{i}{4} = dec2bin(A, 16);
            last_out{i} = bin2dec(regarray{i}{4});
        end
    end
    SR1 = mod(A+1, 8);
    SR2 = 7-mod(A, 8);

    SR1_bin = dec2bin(7-SR1, 3);
    SR2_bin = dec2bin(7-SR2, 3);

    fprintf(fin, '%s\r\n', [dec2bin(A, 16) ' ' LD_REG ' ' RESET ' ' dr_bin ' ' SR1_bin ' ' SR2_bin]);
    fprintf(fout, '%s\r\n', [regarray{SR1+1}{4} ' ' regarray{SR2+1}{4}]);
end

fclose(fin);
fclose(fout);

end