library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all;

entity reltr is
    Port (clk : in std_logic;
        din : in std_logic_vector(3 downto 0);
        dout : out std_logic_vector(3 downto 0));
end reltr;


architecture Behavioral of reltr is

signal add : integer := 0;
signal dv : std_logic := '1';
signal sdout : std_logic_vector(3 downto 0) := (others => '0');
type memory1 is array (0 to 3) of integer;
signal table : memory1 :=
    (0 => 3,
    1 => 2,
    2 => 1,
    3 => 0);

begin

process(clk) begin
    if rising_edge(clk) then
        if add < 3 then
            add <= add + 1;
        else
            add <= 0;
            dv <= '0';
        end if;
    end if;
end process;

process(clk) begin
    if rising_edge(clk) then
        if dv = '1' then
            sdout(add) <= din(table(add));
        end if;
    end if;
end process;

dout <= sdout;

end Behavioral;