-- Łukasz Lech
-- 243 265
-- Deserializer 8-bit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity deserializer is

    port(
        WE, RESET, CLK : in std_logic;
        WY : out std_logic_vector(7 downto 0)
    );

end entity deserializer;

architecture deserial_arch of deserializer is

signal counter : std_logic_vector(2 downto 0) := "000";
signal send : std_logic := '0';
signal reg : std_logic_vector(7 downto 0) := "00000000";

begin

    licznik: process(RESET, CLK)
    begin
        if(RESET = '0') then
            counter <= (others => '0');
        elsif(CLK'event and CLK = '1') then
            counter <= counter + 1;
        end if;
    end process licznik;

    send_reg : process(counter, RESET)
    begin
        if(RESET = '1' and counter = "000") then
            send <= '1';
        else
            send <= '0';
        end if;
    end process send_reg;

    regIsEnabled : process(send, CLK, RESET)
    begin
        if(send = '1') then
            WY(0) <= reg(7);
            WY(1) <= reg(6);
            WY(2) <= reg(5);
            WY(3) <= reg(4);
            WY(4) <= reg(3);
            WY(5) <= reg(2);
            WY(6) <= reg(1);
            WY(7) <= reg(0);
        else
            WY <= (others => '0');
        end if;

        if(RESET = '0') then
            reg <= (others => '0');
        elsif(CLK'event and CLK = '1') then
            reg <= WE & reg(7 downto 1);
        end if;
    end process regIsEnabled;



end architecture deserial_arch;