module accumulator_N_bits
    #(N=8)
    (input [N-1:0] A,
    input clk,
    output [N-1:0] S,
    output overflow, carry);

    (* keep *) wire [N-1:0] B,C;
    (* keep *) wire cout,over;

    register_N_bits #(8) ex_A(A,clk,B);

    adder_N_bits #(8) ex_add(B,S,1'b0,C,cout);

    register_N_bits #(8) ex_S(C,clk,S);
    FFD_posedge ex_cout(cout,clk,carry);
    assign over = cout ^ C[N-1];
    FFD_posedge ex_over(over,clk,overflow);
endmodule

module adder_N_bits
    #(parameter N=4)
    (input [N-1:0] A, B, input CI,
    output [N-1:0] S, output CO);
    wire [N-1:0] c;
    generate
        genvar i;
        for (i=0; i<N; i=i+1)
        begin: ad
                case(i)
                    0:  adder_1_bits x(A[i], B[i], CI, S[i], c[i]);
                    N-1:    adder_1_bits x(A[i], B[i], c[i-1], S[i], CO);
                    default:    adder_1_bits x(A[i], B[i], c[i-1], S[i], c[i]);
                endcase
        end
    endgenerate
endmodule

module FFD_posedge(
    input D,clk,
    output reg Q);

    always @(posedge clk)
        Q <= D;
endmodule

module register_N_bits
    #(N=8)
    (input [N-1:0] D,
    input clk,
    output reg [N-1:0] Q);

    always @(posedge clk)
        Q <= D;
endmodule

module adder_1_bits(
    input a,b,cin,
    output s,cout);

    assign s = a ^ b ^ cin;
    assign cout = a & b & (a ^ b) & cin;
endmodule