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Oct 6th, 2017
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VHDL 0.65 KB | None | 0 0
  1. LIBRARY IEEE;
  2. USE IEEE.STD_LOGIC_1164.ALL;
  3. USE IEEE.STD_LOGIC_ARITH.ALL;
  4. USE IEEE.STD_LOGIC.SIGNED.ALL;
  5.  
  6. ENTITY Execute IS
  7.     PORT(   Read_data_1 : IN    STD_LOGIC_VECTOR ( 31 DOWNTO 0 );
  8.         Read_data_2 : IN    STD_LOGIC_VECTOR ( 31 DOWNTO 0 );
  9.         Sign_extend : IN    STD_LOGIC_VECTOR ( 31 DOWNTO 0 );
  10.         Function_opcode : IN    STD_LOGIC_VECTOR ( 5 DOWNTO 0 );
  11.         ALUOp       : IN    STD_LOGIC_VECTOR ( 1 DOWNTO 0 );
  12.         ALUSrc      : IN    STD_LOGIC;
  13.         Zero        : OUT   STD_LOGIC;
  14.         ALU_Result  : OUT   STD_LOGIC_VECTOR ( 31 DOWNTO 0 );
  15.         Add_Result  : OUT   STD_LOGIC_VECTOR ( 7 DOWNTO 0 );
  16.         PC_plus_4   : IN    STD_LOGIC_VECTOR ( 9 DOWNTO 0 );
  17.         clock, reset    : IN    STD_LOGIC );
  18. END Execute;
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