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Sep 20th, 2019
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  1. .ORG 0x0000
  2. RJMP main
  3.  
  4. main:
  5. LDI r16, 0xFF
  6. OUT DDRD, r16
  7. IN r18, DDRC
  8.  
  9. loop:
  10. LDI r17, 63
  11. OUT PortD, r17
  12. RCALL delay_05
  13. LDI r17, 6
  14. OUT PortD, r17
  15. RCALL delay_05
  16. LDI r17, 91
  17. OUT PortD, r17
  18. RCALL delay_05
  19. LDI r17, 79
  20. OUT PortD, r17
  21. RCALL delay_05
  22. LDI r17, 102
  23. OUT PortD, r17
  24. RCALL delay_05
  25. LDI r17, 109
  26. OUT PortD, r17
  27. RCALL delay_05
  28. LDI r17, 125
  29. OUT PortD, r17
  30. RCALL delay_05
  31. LDI r17, 7
  32. OUT PortD, r17
  33. RCALL delay_05
  34. LDI r17, 127
  35. OUT PortD, r17
  36. RCALL delay_05
  37. LDI r17, 103
  38. OUT PortD, r17
  39. RCALL delay_05
  40. RJMP loop
  41.  
  42. delay_05:
  43. LDI r16, 60
  44.  
  45. outer_loop:
  46. LDI r24, low(3037)
  47. LDI r25, high(3037)
  48.  
  49. delay_loop:
  50. ADIW r24, 1
  51. BRNE delay_loop
  52. DEC r16
  53. BRNE outer_loop
  54. RET
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