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  1. #include "stdio.h"
  2. #include "usbstk5515.h"
  3. #include "aic3204.h"
  4. #include "usbstk5515_i2c.h"
  5. #define XmitL 0x10
  6. #define XmitR 0x20
  7. #define Rcv 0x08
  8. #define AIC3204_I2C_ADDR 0x18
  9. Int16 AIC3204_rget(  Uint16 regnum, Uint16* regval )
  10. {
  11.     Int16 retcode = 0;
  12.     Uint8 cmd[2];
  13.  
  14.     cmd[0] = regnum & 0x007F;       // 7-bit Register Address
  15.     cmd[1] = 0;
  16.  
  17.     retcode |= USBSTK5515_I2C_write( AIC3204_I2C_ADDR, cmd, 1 );
  18.     retcode |= USBSTK5515_I2C_read( AIC3204_I2C_ADDR, cmd, 1 );
  19.  
  20.     *regval = cmd[0];
  21.     USBSTK5515_wait( 10 );
  22.     return retcode;
  23. }
  24.  
  25. /* ------------------------------------------------------------------------ *
  26.  *                                                                          *
  27.  *  _AIC3204_rset( regnum, regval )                                         *
  28.  *                                                                          *
  29.  *      Set codec register regnum to value regval                           *
  30.  *                                                                          *
  31.  * ------------------------------------------------------------------------ */
  32. Int16 AIC3204_rset( Uint16 regnum, Uint16 regval )
  33. {
  34.     Uint8 cmd[2];
  35.     cmd[0] = regnum & 0x007F;       // 7-bit Register Address
  36.     cmd[1] = regval;                // 8-bit Register Data
  37.  
  38.     return USBSTK5515_I2C_write( AIC3204_I2C_ADDR, cmd, 2 );
  39. }
  40.  
  41. void aic3204_intialize( )
  42. {
  43.     /* Configure AIC3204 */
  44.     AIC3204_rset( 0, 0 );      // Select page 0
  45.     AIC3204_rset( 1, 1 );      // Reset codec
  46.     AIC3204_rset( 0, 1 );      // Select page 1
  47.     AIC3204_rset( 1, 8 );      // Disable crude AVDD generation from DVDD
  48.     AIC3204_rset( 2, 1 );      // Enable Analog Blocks, use LDO power
  49.     AIC3204_rset( 0, 0 );
  50.     /* PLL and Clocks config and Power Up  */
  51.     AIC3204_rset( 27, 0x0d );  // BCLK and WCLK are set as o/p; AIC3204(Master)
  52.     AIC3204_rset( 28, 0x00 );  // Data ofset = 0
  53.     AIC3204_rset( 4, 3 );      // PLL setting: PLLCLK <- MCLK, CODEC_CLKIN <-PLL CLK
  54.     AIC3204_rset( 6, 7 );      // PLL setting: J=7
  55.     AIC3204_rset( 7, 0x06 );   // PLL setting: HI_BYTE(D=1680)
  56.     AIC3204_rset( 8, 0x90 );   // PLL setting: LO_BYTE(D=1680)
  57.     AIC3204_rset( 30, 0x88 );  // For 32 bit clocks per frame in Master mode ONLY
  58.                                // BCLK=DAC_CLK/N =(12288000/8) = 1.536MHz = 32*fs
  59.     AIC3204_rset( 5, 0x91 );   // PLL setting: Power up PLL, P=1 and R=1
  60.     AIC3204_rset( 13, 0 );     // Hi_Byte(DOSR) for DOSR = 128 decimal or 0x0080 DAC oversamppling
  61.     AIC3204_rset( 14, 0x80 );  // Lo_Byte(DOSR) for DOSR = 128 decimal or 0x0080
  62.     AIC3204_rset( 20, 0x80 );  // AOSR for AOSR = 128 decimal or 0x0080 for decimation filters 1 to 6
  63.     AIC3204_rset( 11, 0x82 );  // Power up NDAC and set NDAC value to 2
  64.     AIC3204_rset( 12, 0x87 );  // Power up MDAC and set MDAC value to 7
  65.     AIC3204_rset( 18, 0x87 );  // Power up NADC and set NADC value to 7
  66.     AIC3204_rset( 19, 0x82 );  // Power up MADC and set MADC value to 2
  67.     /* DAC ROUTING and Power Up */
  68.     AIC3204_rset( 0, 1 );      // Select page 1
  69.     AIC3204_rset( 0x0c, 8 );   // LDAC AFIR routed to HPL
  70.     AIC3204_rset( 0x0d, 8 );   // RDAC AFIR routed to HPR
  71.     AIC3204_rset( 0, 0 );      // Select page 0
  72.     AIC3204_rset( 64, 2 );     // Left vol=right vol
  73.     AIC3204_rset( 65, 0);      // Left DAC gain to 0dB VOL; Right tracks Left
  74.     AIC3204_rset( 63, 0xd4 );  // Power up left,right data paths and set channel
  75.     AIC3204_rset( 0, 1 );      // Select page 1
  76.     AIC3204_rset( 0x10, 0x00 );// Unmute HPL , 0dB gain
  77.     AIC3204_rset( 0x11, 0x00 );// Unmute HPR , 0dB gain
  78.     AIC3204_rset( 9, 0x30 );   // Power up HPL,HPR
  79.     AIC3204_rset( 0, 0 );      // Select page 0
  80.     USBSTK5515_wait( 100 );    // wait
  81.     /* ADC ROUTING and Power Up */
  82.     AIC3204_rset( 0, 1 );      // Select page 1
  83.     AIC3204_rset( 0x34, 0x30 );// STEREO 1 Jack
  84.                                // IN2_L to LADC_P through 40 kohm
  85.     AIC3204_rset( 0x37, 0x30 );// IN2_R to RADC_P through 40 kohmm
  86.     AIC3204_rset( 0x36, 3 );   // CM_1 (common mode) to LADC_M through 40 kohm
  87.     AIC3204_rset( 0x39, 0xc0 );// CM_1 (common mode) to RADC_M through 40 kohm
  88.     AIC3204_rset( 0x3b, 0 );   // MIC_PGA_L unmute
  89.     AIC3204_rset( 0x3c, 0 );   // MIC_PGA_R unmute
  90.     AIC3204_rset( 0, 0 );      // Select page 0
  91.     AIC3204_rset( 0x51, 0xc0 );// Powerup Left and Right ADC
  92.     AIC3204_rset( 0x52, 0 );   // Unmute Left and Right ADC
  93.  
  94.     AIC3204_rset( 0, 0 );
  95.     USBSTK5515_wait( 200 );    // Wait
  96.  
  97.     /* I2S settings */
  98.     I2S0_SRGR = 0x0;
  99.     I2S0_CR = 0x8010;    // 16-bit word, slave, enable I2S
  100.     I2S0_ICMR = 0x3f;    // Enable interrupts
  101.  
  102.     /* Play Tone */
  103.     /* Disble I2S */
  104.     //I2S0_CR = 0x00;
  105. }
  106. void aic3204_play(uint16_t * sample, uint16_t sample_size){
  107.     int i,j;
  108.     I2S0_SRGR = 0x0;
  109.     I2S0_CR = 0x8010;    // 16-bit word, slave, enable I2S
  110.     I2S0_ICMR = 0x3f;    // Enable interrupts
  111.  
  112.        for ( j = 0 ; j < sample_size ; j++ )
  113.          {
  114.             while((XmitR & I2S0_IR) == 0);        // Wait for transmit interrupt to be pending
  115.             I2S0_W0_MSW_W = (sample[j]) ; // 16 bit left channel transmit audio data
  116.             I2S0_W1_MSW_W = (sample[j]) ; // 16 bit right channel transmit audio data
  117.          }
  118.  
  119.     I2S0_CR = 0x00;
  120. }
  121. void aic3204_sample(uint16_t * sample_L, uint16_t * sample_R,uint16_t sample_size){
  122.     int i;
  123.     I2S0_SRGR = 0x0;
  124.     I2S0_CR = 0x8010;    // 16-bit word, slave, enable I2S
  125.     I2S0_ICMR = 0x3f;    // Enable interrupts
  126.     for(i=0;i<sample_size;i++){
  127.         while((Rcv & I2S0_IR) == 0);  // Wait for interrupt pending flag
  128.         sample_L[i]=I2S0_W0_MSW_R;
  129.         //sample_L[i]|=(I2S0_W0_LSW_R);
  130.         sample_R[i]=(I2S0_W1_MSW_R);
  131.         //sample_R[i]|=(I2S0_W1_LSW_R);
  132.     }
  133.     I2S0_CR = 0x00;
  134. }
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