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- entity mux is
- port(A,B,C : IN BIT;
- s:OUT BIT);
- end mux;
- architecture A1 of mux is
- begin
- s <= a when c='0' else b;
- end A1;
- entity testmux is
- end testmux;
- architecture sim of testmux is
- signal ea,eb,ec:BIT;
- signal s: BIT;
- component mux
- port(a, b, c:in BIT;
- s: OUT BIT);
- end component mux;
- begin
- eb<='0', '1' after 100 ns, '0' after 150 ms;
- ea<='0', '1' after 50 ns, '0' after 120 us;
- ec<='0', '1' after 110 ns;
- M : mux port map(ea,eb,ec,s);
- end sim;
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