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Feb 17th, 2020
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  1. entity mux is
  2. port(A,B,C : IN BIT;
  3. s:OUT BIT);
  4. end mux;
  5.  
  6. architecture A1 of mux is
  7. begin
  8. s <= a when c='0' else b;
  9. end A1;
  10.  
  11. entity testmux is
  12. end testmux;
  13.  
  14. architecture sim of testmux is
  15. signal ea,eb,ec:BIT;
  16. signal s: BIT;
  17. component mux
  18. port(a, b, c:in BIT;
  19. s: OUT BIT);
  20. end component mux;
  21. begin
  22. eb<='0', '1' after 100 ns, '0' after 150 ms;
  23. ea<='0', '1' after 50 ns, '0' after 120 us;
  24. ec<='0', '1' after 110 ns;
  25. M : mux port map(ea,eb,ec,s);
  26. end sim;
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