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  1. --clock 2hz
  2.  
  3. library IEEE;
  4. use IEEE.STD_LOGIC_1164.ALL;
  5.  
  6. entity clock2hz is
  7. port(
  8. clockIn: in std_logic;
  9. clockOut: out std_logic);
  10.  
  11. end clock2hz;
  12.  
  13. architecture action of clock2hz is
  14.  
  15. signal counter : integer:=1;
  16. signal temp: std_logic := '0';
  17.  
  18. begin
  19. process(clockIn)
  20. begin
  21. if(clockIn'event and clockIn='1') then
  22. counter <=counter + 1;
  23. if (counter=12500000)then
  24. temp <= NOT temp;
  25. counter <= 1;
  26. end if;
  27. end if;
  28. clockOut <= temp;
  29. end process;
  30. end architecture;
  31.  
  32. --------sr
  33.  
  34. library IEEE;
  35. use IEEE.STD_LOGIC_1164.ALL;
  36. entity przerzutnik_SR is
  37. Port ( S : in STD_LOGIC;
  38. R : in STD_LOGIC;
  39. clock: in STD_LOGIC;
  40. Q : out STD_LOGIC;
  41. notQ : out STD_LOGIC);
  42. end przerzutnik_SR;
  43. architecture Behavioral of przerzutnik_SR is
  44. signal Q2 : STD_LOGIC;
  45. signal notQ2 : STD_LOGIC;
  46. begin
  47. process(clock)
  48. begin
  49. if clock'event and clock='1' then
  50. Q <= Q2;
  51. Q2 <= R nor notQ2;
  52. notQ2 <= S nor Q2;
  53. notQ <= not Q2;
  54. end if;
  55. end process;
  56. end architecture;
  57.  
  58. ------multiplekser
  59.  
  60. library ieee;
  61. use ieee.std_logic_1164.all;
  62. use ieee.std_logic_unsigned.all;
  63. entity multiplexer is
  64. port (
  65. clock1, clock2: in std_logic;
  66. S0: in std_logic;
  67. wyj: out std_logic
  68. );
  69. end multiplexer;
  70. architecture bhv of multiplexer is
  71. begin
  72. process (clock1, clock2, S0) is
  73. begin
  74. if (S0 ='0') then
  75. wyj <= clock2;
  76. else
  77. wyj <= clock1;
  78. end if;
  79. end process;
  80. end architecture;
  81.  
  82.  
  83. ------licznik sek
  84.  
  85. library ieee;
  86. use ieee.std_logic_1164.all;
  87. use ieee.std_logic_unsigned.all;
  88.  
  89. entity licznik_s is
  90. port (
  91. clk,start,us,min_zero : in std_logic;
  92. licz_sek_jed,licz_sek_dz: out std_logic_vector (3 downto 0);
  93. dioda_koniec : out std_logic);
  94. end licznik_s;
  95.  
  96. architecture licz_sek of licznik_s is
  97. signal sek_jed : std_logic_vector (3 downto 0);
  98. signal sek_dzi : std_logic_vector (3 downto 0);
  99.  
  100. begin
  101.  
  102. process(clk)
  103. begin
  104. if rising_edge (clk) then
  105. --dekrementacja
  106. if start='1' then
  107.  
  108. if sek_jed/="0000" then
  109. sek_jed<=(sek_jed-'1');
  110.  
  111. else
  112. if sek_dzi/="0000" then
  113. sek_jed<="1001";
  114. sek_dzi<=(sek_dzi-'1');
  115.  
  116. else
  117. if min_zero = '0' then
  118. sek_dzi<="0101";
  119. sek_jed<="1001";
  120.  
  121. end if;
  122. end if;
  123. end if;
  124. end if;
  125.  
  126.  
  127. --inkrementacja
  128. if start='0' then
  129. if us = '1' then
  130. if sek_jed/="1001" then
  131. sek_jed<=(sek_jed+'1');
  132. else
  133. if sek_dzi/="0101" then
  134. sek_dzi<=(sek_dzi + '1');
  135. sek_jed<="0000";
  136. else
  137. sek_dzi<="0000";
  138. sek_jed<="0000";
  139. end if;
  140. end if;
  141. end if;
  142. end if;
  143. end if;
  144. --sprawdzanie czy jest zero
  145. if falling_edge (clk) then
  146. if sek_dzi="0000" and sek_jed="0000" then
  147. dioda_koniec<='1';
  148. else
  149. dioda_koniec<='0';
  150. end if;
  151.  
  152. end if;
  153. licz_sek_jed<= sek_jed;
  154. licz_sek_dz<=sek_dzi;
  155.  
  156.  
  157. end process;
  158. end architecture;
  159.  
  160.  
  161. -----licznik min
  162.  
  163.  
  164. library ieee;
  165. use ieee.std_logic_1164.all;
  166. use ieee.std_logic_unsigned.all;
  167. entity licznik_m is
  168. port (
  169. clk,start,um,przepel : in std_logic;
  170. licz_min_jed,licz_min_dz: out std_logic_vector (3 downto 0);
  171. dioda_koniec : out std_logic);
  172. end licznik_m;
  173.  
  174. architecture licz_min of licznik_m is
  175. signal min_jed : std_logic_vector (3 downto 0);
  176. signal min_dzi : std_logic_vector (3 downto 0);
  177.  
  178. begin
  179. process(clk)
  180. begin
  181.  
  182. if rising_edge (clk) then
  183. --dekrementacja
  184. if start='1' then
  185. if przepel='1' then
  186.  
  187. if min_jed/="0000" then
  188. min_jed<=(min_jed-'1');
  189. else
  190. if min_dzi/="0000" then
  191. min_jed<="1001";
  192. min_dzi <= (min_dzi - '1');
  193. end if;
  194. end if;
  195. end if;
  196. end if;
  197. --inkrementacja
  198. if start='0' then
  199. if um='1' then
  200. if min_jed/="1001" then
  201. min_jed<=(min_jed+'1');
  202. else
  203. if min_dzi/="0101" then
  204. min_dzi<=(min_dzi+'1');
  205. min_jed<="0000";
  206. else
  207. min_dzi<="0000";
  208. min_jed<="0000";
  209. end if;
  210. end if;
  211. end if;
  212. end if;
  213. --sprawdzenie zera
  214. if min_dzi="0000" and min_jed="0000" then
  215. dioda_koniec<='1';
  216. else
  217. dioda_koniec<='0';
  218. end if;
  219. end if;
  220. licz_min_jed<=min_jed;
  221. licz_min_dz<=min_dzi;
  222.  
  223. end process;
  224. end architecture;
  225.  
  226.  
  227. ------bcd sekjed
  228. library ieee;
  229. use ieee.std_logic_1164.all;
  230. use ieee.std_logic_unsigned.all;
  231.  
  232. entity bcdTo7segJed is
  233. port (
  234. licz_sek_jed_in : in std_logic_vector (3 downto 0);
  235. segment7 : out std_logic_vector(6 downto 0));
  236. end bcdTo7segJed;
  237.  
  238. architecture translate of bcdTo7segJed is
  239. begin
  240. process(licz_sek_jed_in)
  241. begin
  242. case licz_sek_jed_in is
  243. when "0000"=> segment7 <="1000000"; -- '0'
  244. when "0001"=> segment7 <="1111001"; -- '1'
  245. when "0010"=> segment7 <="0100100"; -- '2'
  246. when "0011"=> segment7 <="0110000"; -- '3'
  247. when "0100"=> segment7 <="0011001"; -- '4'
  248. when "0101"=> segment7 <="0010010"; -- '5'
  249. when "0110"=> segment7 <="0000010"; -- '6'
  250. when "0111"=> segment7 <="1111000"; -- '7'
  251. when "1000"=> segment7 <="0000000"; -- '8'
  252. when "1001"=> segment7 <="0011000"; -- '9'
  253. when others=> segment7 <="0111111";
  254. end case;
  255. end process;
  256. end architecture;
  257.  
  258.  
  259. ---bcd sekdz
  260.  
  261. library ieee;
  262. use ieee.std_logic_1164.all;
  263. use ieee.std_logic_unsigned.all;
  264.  
  265. entity bcdTo7seg_sekDZ is
  266. port (
  267. licz_sek_dz_in : in std_logic_vector (3 downto 0);
  268. segment7_sekDz : out std_logic_vector(6 downto 0));
  269. end bcdTo7seg_sekDZ;
  270.  
  271. architecture translate of bcdTo7seg_sekDZ is
  272. begin
  273. process(licz_sek_dz_in)
  274. begin
  275. case licz_sek_dz_in is
  276. when "0000"=> segment7_sekDz <="1000000"; -- '0'
  277. when "0001"=> segment7_sekDz <="1111001"; -- '1'
  278. when "0010"=> segment7_sekDz <="0100100"; -- '2'
  279. when "0011"=> segment7_sekDz <="0110000"; -- '3'
  280. when "0100"=> segment7_sekDz <="0011001"; -- '4'
  281. when "0101"=> segment7_sekDz <="0010010"; -- '5'
  282. when "0110"=> segment7_sekDz <="0000010"; -- '6'
  283. when others=> segment7_sekDz <="0111111";
  284. end case;
  285. end process;
  286. end architecture;
  287.  
  288.  
  289. ----bcd minjed
  290.  
  291. library ieee;
  292. use ieee.std_logic_1164.all;
  293. use ieee.std_logic_unsigned.all;
  294.  
  295. entity bcdTo7seg_minJed is
  296. port (
  297. licz_min_jed_in: in std_logic_vector (3 downto 0);
  298. segment7_minJed : out std_logic_vector(6 downto 0));
  299. end bcdTo7seg_minJed;
  300.  
  301. architecture translate of bcdTo7seg_minJed is
  302. begin
  303. process(licz_min_jed_in)
  304. begin
  305. case licz_min_jed_in is
  306. when "0000"=> segment7_minJed <="1000000"; -- '0'
  307. when "0001"=> segment7_minJed <="1111001"; -- '1'
  308. when "0010"=> segment7_minJed <="0100100"; -- '2'
  309. when "0011"=> segment7_minJed <="0110000"; -- '3'
  310. when "0100"=> segment7_minJed <="0011001"; -- '4'
  311. when "0101"=> segment7_minJed <="0010010"; -- '5'
  312. when "0110"=> segment7_minJed <="0000010"; -- '6'
  313. when "0111"=> segment7_minJed <="1111000"; -- '7'
  314. when "1000"=> segment7_minJed <="0000000"; -- '8'
  315. when "1001"=> segment7_minJed <="0011000"; -- '9'
  316. when others=> segment7_minJed <="0111111";
  317. end case;
  318. end process;
  319. end architecture;
  320.  
  321.  
  322. ----bcd mindz
  323.  
  324. library ieee;
  325. use ieee.std_logic_1164.all;
  326. use ieee.std_logic_unsigned.all;
  327.  
  328. entity bcdTo7seg_minDZ is
  329. port (
  330. licz_min_dz_in : in std_logic_vector (3 downto 0);
  331. segment7_minDz : out std_logic_vector(6 downto 0)); --WYJSCIA 7SEG
  332. end bcdTo7seg_minDZ;
  333.  
  334. architecture translate of bcdTo7seg_minDZ is
  335. begin
  336. process(licz_min_dz_in)
  337. begin
  338.  
  339.  
  340.  
  341.  
  342.  
  343.  
  344. case licz_min_dz_in is
  345. when "0000"=> segment7_minDz <="1000000"; -- '0'
  346. when "0001"=> segment7_minDz <="1111001"; -- '1'
  347. when "0010"=> segment7_minDz <="0100100"; -- '2'
  348. when "0011"=> segment7_minDz <="0110000"; -- '3'
  349. when "0100"=> segment7_minDz <="0011001"; -- '4'
  350. when "0101"=> segment7_minDz <="0010010"; -- '5'
  351. when "0110"=> segment7_minDz <="0000010"; -- '6'
  352. --wszystko poza zakresem 0-9 wyswietla kreskÄ™ "-"
  353. when others=> segment7_minDz <="0111111";
  354. end case;
  355. end process;
  356. end architecture;
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