kwpuc2

--clock 2hz

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity clock2hz is
		port(
		clockIn: in std_logic;
		clockOut: out std_logic);

end clock2hz;

architecture action of clock2hz is

 signal counter : integer:=1;
 signal temp: std_logic := '0';

 begin
		process(clockIn)
			begin
			if(clockIn'event and clockIn='1') then
			counter <=counter + 1;
			if (counter=12500000)then
			temp <= NOT temp;
			counter <= 1;
			end if;
			end if;
			clockOut <= temp;
			end process;
			end architecture;

 --------sr

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity przerzutnik_SR is
    Port ( S : in    STD_LOGIC;
           R : in    STD_LOGIC;
			  clock: in STD_LOGIC;
           Q : out   STD_LOGIC;
			  notQ : out STD_LOGIC);
end przerzutnik_SR;
architecture Behavioral of przerzutnik_SR is
signal Q2   : STD_LOGIC;
signal notQ2 : STD_LOGIC;
begin
process(clock)
	begin
	if clock'event and clock='1' then
		Q    <= Q2;
		Q2   <= R nor notQ2;
		notQ2 <= S nor Q2;
		notQ <= not Q2;
	end if;
end process;
end architecture;

------multiplekser

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity multiplexer is
port (
clock1, clock2: in std_logic;
S0: in std_logic;
wyj: out std_logic
);
end multiplexer;
architecture bhv of multiplexer is
begin
process (clock1, clock2, S0) is
begin
  if (S0 ='0') then
      wyj <= clock2;
  else
      wyj <= clock1;
  end if;
end process;
end architecture;


------licznik sek

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity licznik_s is
port (
clk,start,us,min_zero : in std_logic;
licz_sek_jed,licz_sek_dz: out std_logic_vector (3 downto 0);
dioda_koniec : out std_logic);
end licznik_s;

architecture licz_sek of licznik_s is
signal sek_jed : std_logic_vector (3 downto 0);
signal sek_dzi : std_logic_vector (3 downto 0);

begin

process(clk)
begin
if rising_edge (clk) then
--dekrementacja
		if start='1'  then

			if sek_jed/="0000" then
			sek_jed<=(sek_jed-'1');

			else
				if sek_dzi/="0000" then
				sek_jed<="1001";
				sek_dzi<=(sek_dzi-'1');

				else
					if min_zero = '0' then
					sek_dzi<="0101";
					sek_jed<="1001";

					end if;
				end if;
			end if;
		end if;


--inkrementacja
	if start='0' then
		if us = '1' then
			if sek_jed/="1001" then
			sek_jed<=(sek_jed+'1');
			else
				if sek_dzi/="0101" then
				sek_dzi<=(sek_dzi + '1');
				sek_jed<="0000";
				else
				sek_dzi<="0000";
				sek_jed<="0000";
				end if;
			end if;
		end if;
	end if;
end if;
--sprawdzanie czy jest zero
if falling_edge (clk) then
if sek_dzi="0000" and sek_jed="0000" then
dioda_koniec<='1';
else
dioda_koniec<='0';
end if;

end if;
licz_sek_jed<= sek_jed;
licz_sek_dz<=sek_dzi;


end process;
end architecture;


-----licznik min


library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity licznik_m is
port (
clk,start,um,przepel : in std_logic;
licz_min_jed,licz_min_dz: out std_logic_vector (3 downto 0);
dioda_koniec  : out std_logic);
end licznik_m;

architecture licz_min of licznik_m is
signal min_jed : std_logic_vector (3 downto 0);
signal min_dzi : std_logic_vector (3 downto 0);

begin
process(clk)
begin

if rising_edge (clk) then
--dekrementacja
	if start='1' then
		if przepel='1'  then

				if min_jed/="0000" then
					min_jed<=(min_jed-'1');
					else
						if min_dzi/="0000" then
						min_jed<="1001";
						min_dzi <= (min_dzi - '1');
						end if;
				end if;
		end if;
	end if;
--inkrementacja
	if start='0' then
		if um='1' then
			if min_jed/="1001" then
			min_jed<=(min_jed+'1');
			else
				if min_dzi/="0101" then
				min_dzi<=(min_dzi+'1');
				min_jed<="0000";
				else
				min_dzi<="0000";
				min_jed<="0000";
				end if;
			end if;
		end if;
	end if;
--sprawdzenie zera
if min_dzi="0000" and min_jed="0000" then
dioda_koniec<='1';
else
dioda_koniec<='0';
end if;
end if;
licz_min_jed<=min_jed;
licz_min_dz<=min_dzi;

end process;
end architecture;


------bcd sekjed
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bcdTo7segJed is
port (
licz_sek_jed_in : in std_logic_vector (3 downto 0);
segment7 : out std_logic_vector(6 downto 0));
end bcdTo7segJed;

architecture translate of bcdTo7segJed is
begin
process(licz_sek_jed_in)
begin
case  licz_sek_jed_in is
when "0000"=> segment7 <="1000000";  -- '0'
when "0001"=> segment7 <="1111001";  -- '1'
when "0010"=> segment7 <="0100100";  -- '2'
when "0011"=> segment7 <="0110000";  -- '3'
when "0100"=> segment7 <="0011001";  -- '4'
when "0101"=> segment7 <="0010010";  -- '5'
when "0110"=> segment7 <="0000010";  -- '6'
when "0111"=> segment7 <="1111000";  -- '7'
when "1000"=> segment7 <="0000000";  -- '8'
when "1001"=> segment7 <="0011000";  -- '9'
when others=> segment7 <="0111111";
end case;
end process;
end architecture;


---bcd sekdz

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bcdTo7seg_sekDZ is
port (
licz_sek_dz_in : in std_logic_vector (3 downto 0);
segment7_sekDz : out std_logic_vector(6 downto 0));
end bcdTo7seg_sekDZ;

architecture translate of bcdTo7seg_sekDZ is
begin
process(licz_sek_dz_in)
begin
case  licz_sek_dz_in is
when "0000"=> segment7_sekDz <="1000000";  -- '0'
when "0001"=> segment7_sekDz <="1111001";  -- '1'
when "0010"=> segment7_sekDz <="0100100";  -- '2'
when "0011"=> segment7_sekDz <="0110000";  -- '3'
when "0100"=> segment7_sekDz <="0011001";  -- '4'
when "0101"=> segment7_sekDz <="0010010";  -- '5'
when "0110"=> segment7_sekDz <="0000010";  -- '6'
when others=> segment7_sekDz <="0111111";
end case;
end process;
end architecture;


----bcd minjed

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bcdTo7seg_minJed is
port (
licz_min_jed_in: in std_logic_vector (3 downto 0);
segment7_minJed : out std_logic_vector(6 downto 0));
end bcdTo7seg_minJed;

architecture translate of bcdTo7seg_minJed is
begin
process(licz_min_jed_in)
begin
case  licz_min_jed_in is
when "0000"=> segment7_minJed <="1000000";  -- '0'
when "0001"=> segment7_minJed <="1111001";  -- '1'
when "0010"=> segment7_minJed <="0100100";  -- '2'
when "0011"=> segment7_minJed <="0110000";  -- '3'
when "0100"=> segment7_minJed <="0011001";  -- '4'
when "0101"=> segment7_minJed <="0010010";  -- '5'
when "0110"=> segment7_minJed <="0000010";  -- '6'
when "0111"=> segment7_minJed <="1111000";  -- '7'
when "1000"=> segment7_minJed <="0000000";  -- '8'
when "1001"=> segment7_minJed <="0011000";  -- '9'
when others=> segment7_minJed <="0111111";
end case;
end process;
end architecture;


----bcd mindz

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity bcdTo7seg_minDZ is
port (
licz_min_dz_in : in std_logic_vector (3 downto 0);
segment7_minDz : out std_logic_vector(6 downto 0));  --WYJSCIA 7SEG
end bcdTo7seg_minDZ;

architecture translate of bcdTo7seg_minDZ is
begin
process(licz_min_dz_in)
begin






case  licz_min_dz_in is
when "0000"=> segment7_minDz <="1000000";  -- '0'
when "0001"=> segment7_minDz <="1111001";  -- '1'
when "0010"=> segment7_minDz <="0100100";  -- '2'
when "0011"=> segment7_minDz <="0110000";  -- '3'
when "0100"=> segment7_minDz <="0011001";  -- '4'
when "0101"=> segment7_minDz <="0010010";  -- '5'
when "0110"=> segment7_minDz <="0000010";  -- '6'
 --wszystko poza zakresem 0-9 wyswietla kreskę "-"
when others=> segment7_minDz <="0111111";
end case;
end process;
end architecture;